Apparatuses and methods for shared row and column address buses

Patent metadata

Field	Value
Publication number	US-12346586-B2
Application number	US-202318480773-A
Country	US
Kind code	B2
Filing date	Oct 4, 2023
Priority date	Dec 13, 2022
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

Apparatuses and methods for shared row and column address buses. Row and column addresses are distributed along separate respective global buses in a central logic region of a memory. The row and column addresses are coupled through a shared address bus from the central logic region to a bank logic region. For example the row address may be provided along the shared address bus at a first time and the column address may be provided along the shared address bus at a second time.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of memory banks;
a first latch configured to receive a row address from a row address bus, wherein the row address is associated with a row of a memory bank of the plurality of memory banks;
a second latch configured to receive a column address from a column address bus, wherein the column address is associated with a column of the memory bank of the plurality of memory banks, and wherein the first latch and the second latch are located in a central logic region;
a multiplexer configured to provide the row address from the first latch at a first time and the column address from the second latch at a second time, wherein the row address and the column address are provided along a shared bus from the central logic region to a bank logic region of the memory bank;
a third latch configured to receive the row address from the shared bus; and
a fourth latch configured to receive the column address from the shared bus, wherein the third latch and the fourth latch are in the bank logic region of the memory bank.

2. The apparatus of claim 1 , further comprising:
a row decoder configured to activate a word line in the memory bank based on the row address in the third latch; and
a column decoder configured to activate one or more bit lines in the memory bank based on the column address in the fourth latch.

3. The apparatus of claim 1 , wherein the multiplexer is configured to provide the row address responsive to a row activation signal and wherein the multiplexer is configured to provide the column address responsive to a read or write signal.

4. The apparatus of claim 1 , wherein the row address bus and the column address bus are located in the central logic region.

5. The apparatus of claim 1 , wherein the shared bus has a number of conductive elements less than a number of bits in the row address plus a number of bits in the column address.

6. The apparatus of claim 1 , further comprising a command/address decoder configured to provide the row address along the row address bus and the column address along the column address bus, wherein the command/address decoder is located in the central logic region.

7. An apparatus comprising:
a plurality of memory banks;
a bank logic region associated with a memory bank of the plurality of memory banks;
a central logic region including a row address bus and a column address bus;
a shared address bus coupling the central logic region to the bank logic region;
a multiplexer configured to selectively couple the row address bus or the column address bus to the shared address bus;
a first address latch configured to latch a row address off the row address bus, wherein the row address is associated with a row of the memory bank; and
a second address latch configured to latch a column address off the column address bus, wherein the column address is associated with a column of the memory bank, and wherein the multiplexer is configured to couple the row address from the first address latch to the shared address bus at a first time and the column address from the second address latch to the shared address bus at a second time.

8. The apparatus of claim 7 , further comprising a command/address decoder configured to provide t row address along the row address bus and the column address along the column address bus.

9. The apparatus of claim 7 , wherein the row address bus includes a first number of conductive elements, the column address bus includes a second number of conductive elements, and the shared address bus includes a third number of conductive elements, wherein the third number is less than a sum of the first number and the second number.

10. The apparatus of claim 9 , wherein the third number is the lesser of the first number or the second number.

11. The apparatus of claim 7 , wherein the multiplexer is configured to couple the row address bus to the shared address bus responsive to a row activation signal and configured to couple the column address bus to the shared address bus responsive to a read or write signal.

12. The apparatus of claim 7 , further comprising:
a second bank logic region associated with a second memory bank;
a second shared address bus coupling the central logic region to the second bank logic region; and
a second multiplexer configured to couple the row address bus or the column address bus to the second shared address bus.

13. A method comprising:
providing a row address along a row address bus in a central logic region , wherein the row address is associated with a row of a memory bank of a plurality of memory banks;
providing, by a multiplexer, the row address along a shared bus from the central logic region to a bank logic region of the memory bank responsive to a row activation signal at a first time;
providing a column address along a column address bus in the central logic region, wherein the column address is associated with a column of the memory bank; and
providing, by the multiplexer, column address along the shared bus from the central logic region to the bank logic region responsive to a read or write command at a second time.

14. The method of claim 13 , further comprising providing the row address along the row address bus and the column address along the column address bus responsive to an access operation.

15. The method of claim 13 , further comprising:
selecting the row of the memory bank associated with the bank logic region based on the row address;
activating the selected row responsive to the row activation signal;
selecting the column the memory bank based on the column address; and
accessing the selected column responsive to the read or write command.

16. The method of claim 13 further comprising:
generating a multiplexer select signal which changes from a first level to a second level responsive to the read or write command and which resets to the first level responsive to a precharge command;
providing the row address to the shared bus with the multiplexer when the multiplexer select signal is at the first level; and
providing the column address to the shared address-bus with the multiplexer when the multiplexer select signal is at the second level.

17. The method of claim 16 further comprising:
latching the row address in a first address latch responsive to the row activation command;
latching the column address in a second address latch responsive to the read or write command; and
coupling the first address latch or the second address latch to the address bus with the multiplexer based on A state of the multiplexer select signal.

18. The method of claim 13 , further comprising providing the row address along a plurality of conductive elements of the shared bus and providing the column address along less than all of the plurality of conductive elements.

19. The apparatus of claim 1 , wherein the multiplexer is configured to receive a multiplexer control signal, wherein the multiplexer is configured to provide the row address along the shared bus when the multiplexer control signal is at an inactive level, and wherein the multiplexer is configured to provide the column address along the shared bus when the multiplexer control signal is at an active level.

Assignees

• Micron Technology Inc

Inventors

• Akamatsu Hiroshi
• Pradhan Reuben

Classifications

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/064 Primary

  Management of blocks · CPC title