Apparatuses for sense amplifier voltage control

Patent metadata

Field	Value
Publication number	US-12165695-B2
Application number	US-202217737999-A
Country	US
Kind code	B2
Filing date	May 5, 2022
Priority date	May 5, 2022
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of array access control circuits, each array access control circuit of the plurality of array access control circuits configured to receive a respective one of a plurality of section enable signals and each array access control circuit of the plurality of array access control circuits further configured to receive an access control signal, each array access control circuit of the plurality of array access control circuits is configured to provide a section access control signal responsive to the access control signal when the respective section enable signal is in an active state, wherein each array access control circuit of the plurality of array access control circuits corresponds to a respective section of a plurality of sections in a bank; and
a level shifter circuit coupled to the plurality of array access control circuits and configured to receive a control signal and further configured to provide the plurality of array access control circuits with the access control signal responsive to the control signal,
wherein a first logic level of the control signal is represented by a first power supply voltage and wherein a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage, and
wherein the level shifter circuit is shared across the plurality of sections in the bank.

2. The apparatus of claim 1 , further comprising a bank logic circuit configured to receive bank address signals and a command and further configured to provide row address signals responsive to the bank address signals corresponding to the bank logic circuit,
wherein the bank logic circuit comprises the level shifter circuit configured to provide the access control signal responsive to the bank address signals corresponding to the bank logic circuit, the access control signal provided by the level shifter circuit having an activation timing based receipt of the command.

3. The apparatus of claim 2 , further comprising a row decoder circuit configured to receive the row address signals and further configured to provide the plurality of section enable signals responsive to the row address signals,
wherein the row decoder circuit comprises the plurality of array access control circuits.

4. The apparatus of claim 1 , further comprising a memory cell array including a plurality of banks.

5. The apparatus of claim 4 , further comprising sense amplifiers coupled to memory cells in a section of the plurality of sections, and
wherein the array access control circuit corresponding to the section is configured to provide the section access control signal to the sense amplifiers.

6. An apparatus comprising:
a level shifter configured to receive a first section enable signal and further configured to provide a second section enable signal responsive to the first section enable signal, wherein the level shifter is shared across a plurality of sections in a bank; and
a plurality of section enable circuits, each section enable circuit of the plurality of section enable circuits configured to receive the second section enable signal and a respective control signal of a plurality of control signals, each section enable circuit of the plurality of section enable circuits is configured to provide a section control signal responsive to the respective first control signal when the second section enable signal in an active state, wherein the plurality of section enable circuits is included in an array access control circuit of a plurality of array access control circuits, each array access control circuit of the plurality of array access control circuits corresponding to a respective section of the plurality of sections in the bank, and
wherein a first logic level of the first section enable signal is represented by a first power supply voltage and wherein a first logic level of the second section enable signal is represented by a second power supply voltage greater than the first power supply voltage.

7. The apparatus of claim 6 , further comprising a row decoder configured to receive row address signals and further configured to provide a plurality of section enable signals including the first and second enable signals responsive to the row address signals,
wherein the row decoder circuit comprises:
a plurality of level shifters including the level shifter, the plurality of level shifter circuits configured to receive the respective plurality of section enable signals.

8. The apparatus of claim 7 , further comprising a plurality of banks,
wherein a bank of the plurality of banks comprises a plurality of sections, and
wherein the plurality of section enable circuits are configured to provide the plurality of second control signals responsive to a corresponding section enable signal of the plurality of section enable signals.

9. The apparatus of claim 8 , further comprising sense amplifiers coupled to memory cells in the corresponding section of the plurality of sections,
wherein the plurality of section enable circuits are configured to provide the sense amplifiers with the plurality of second control signals responsive to the corresponding section enable signal of the plurality of section enable signals.

10. An apparatus comprising:
a first array access control circuit configured to receive an access control signal and a first section enable signal and further configured to provide a first section control signal responsive to the access control signal when the first section enable signal is in an active state, wherein the first array access control circuit corresponds to a first section of a plurality of sections in a bank:
a second array access control circuit configured to receive the access control signal and a second section enable signal and further configured to provide a second section control signal responsive to the access control signal when the second section enable signal is in an active state, wherein the second array access control circuit corresponds to a second section of the plurality of sections in the bank; and
a level shifter circuit configured to receive a control signal and further configured to provide the access control signal responsive to the control signal,
wherein a first logic level of the control signal is represented by a first power supply voltage and wherein a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage, and
wherein the level shifter circuit is shared across the plurality of sections in the bank.

11. The apparatus of claim 10 , wherein the level shifter circuit is disposed between the first and second array access control circuits.

12. The apparatus of claim 10 , wherein each array access control circuit of the first and second array access control circuits comprises:
a first inverter configured to receive the access control signal and further configured to provide a first internal control signal when the first inverter is enabled; and
a second inverter configured to provide a second internal control signal that is a complementary signal of the first internal control signal.

13. An apparatus comprising:
a first array access control circuit configured to receive an access control sigual and a first section enable signal and further configured to provide a first section control signal responsive to the access control signal when the first section enable signal is in an active state;
a second array access control circuit configured to receive the access control signal and a second section enable signal and further configured

Assignees

• Micron Technology Inc

Inventors

• Park Sang-Kyun
• He Yuan
• Akamatsu Hiroshi

Classifications

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title