Apparatuses and methods including dice latches in a semiconductor device

Patent metadata

Field	Value
Publication number	US-12394456-B2
Application number	US-202318335385-A
Country	US
Kind code	B2
Filing date	Jun 15, 2023
Priority date	Jan 13, 2022
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of dice latches coupled in parallel and configured to latch respective data;
dice latch control logic configured to receive a load control signal and a reset control signal and further configured to provide a reset signal and further provide first and second load signals to the plurality of dice latches, the reset signal based on the reset control signal and the first and second load signals based on the load control signal and the reset control signal; and
a plurality of data input logic, each coupled to a respective one of the plurality of dice latches, each of the plurality of data input logic configured to receive a precharge control signal and respective input data and further configured to provide data and complementary data to the respective one of the plurality of dice latches.

2. The apparatus of claim 1 , wherein the data and complementary data have complementary logic levels based on the input data when the precharge control signal is inactive.

3. The apparatus of claim 2 , wherein the data and complementary data have the same logic level when the precharge control signal is active.

4. The apparatus of claim 1 , wherein the dice latch control logic comprises first load control logic configured to provide an active first load signal and second load control logic configured to provide an active second load signal when the load control signal is active and the reset control signal is inactive.

5. The apparatus of claim 4 , wherein the dice latch control logic is further configured to provide the active first and second load signals when the reset control signal is active regardless of a state of the load control signal.

6. The apparatus of claim 5 , wherein the dice latch control logic further comprises reset control logic configured to provide the reset signal having a logic level complementary to a logic level of the reset control signal.

7. The apparatus of claim 1 , wherein the dice latch control logic further comprises reset control logic configured to provide the reset signal having a logic level complementary to a logic level of the reset control signal.

8. The apparatus of claim 1 , wherein a data input logic of the plurality of data input logic comprises:
first data logic configured to provide the data having a same logic level as the input data when the precharge control signal is inactive; and
second data logic configured to provide the complementary data having a logic level complementary to the input data when the precharge control signal is inactive.

9. The apparatus of claim 8 , wherein the first data logic and the second data logic are further configured to provide the data and complementary data having the same logic level when the precharge control signal is active.

10. The apparatus of claim 1 , wherein a dice latch of the plurality of dice latches coupled in parallel comprises:
a latch circuit configured including first and second data nodes, and third and fourth data nodes;
first and second data node switches coupled to the first and second data nodes, respectively, the first data node switch configured to provide the data from the respective data input logic to the first data node when activated by an active first load signal and the second data node switch configured to provide the data from the respective data input logic to the second data node when activated by an active second load signal; and
third and fourth data node switches coupled to the third and fourth data nodes, respectively, the third data node switch configured to provide the complementary data from the respective data input logic to the third data node when activated by the active first load signal and the fourth data node switch configured to provide the complementary data from the respective data input logic to the fourth data node when activated by the active second load signal.

11. The apparatus of claim 10 , wherein the latch circuit is further configured to latch the data at the first and second data nodes and to latch the complementary data at the third and fourth data nodes when the data and complementary data are provided by the respective data node switch.

12. The apparatus of claim 11 , wherein the latch circuit comprises:
a first reset circuit configured to reduce a load from the third data node when activated by an active reset signal; and
a second reset circuit configured to reduce a load from the fourth data node when activated by the active reset signal.

13. The apparatus of claim 12 wherein the latch circuit further comprises:
a first pull-up circuit and a first pull-down circuit coupled to the first data node;
a second pull-up circuit and a second pull-down circuit coupled to the second data node;
a third pull-up circuit and a third pull-down circuit coupled to the third data node; and
a fourth pull-up circuit and a fourth pull-down circuit coupled to the fourth data node,
wherein the first reset circuit is coupled to the third pull-down circuit and configured to be provided a logic level voltage, and
wherein the second reset circuit is coupled to the fourth pull-down circuit and configured to be provided the logic level voltage.

Assignees

• Micron Technology Inc

Inventors

• Riho Yoshiro
• Akamatsu Hiroshi
• Long Jian
• Werhane Kevin G
• Liu Liang
• Fujiwara Yoshinori

Classifications

• H03K3/037

  Bistable circuits · CPC title

• G11C5/025

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• G11C5/005

  Circuit means for protection against loss of information of semiconductor storage devices · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C7/1087 Primary

  Data input latches · CPC title