Packaged semiconductor device and method of fabricating a packaged semiconductor device
US-2017373016-A1 · Dec 28, 2017 · US
Interconnections on sidewalls of containers
Interconnections on sidewalls of containers · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W72/801 |
| Official title | {Interconnections on sidewalls of containers} |
| Display label | Interconnections on sidewalls of containers |
| Total patents | 184 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly growing.
| Year | Patents |
|---|---|
| 2015 | 20 |
| 2016 | 30 |
| 2017 | 20 |
| 2018 | 14 |
| 2019 | 18 |
| 2020 | 13 |
| 2021 | 5 |
| 2022 | 12 |
| 2023 | 17 |
| 2024 | 17 |
| 2025 | 14 |
| 2026 | 4 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Module stacking mechanism with integrated ground
US-2017345803-A1 · Nov 30, 2017 · US
Microelectronic packages having stacked die and wire bond interconnects
US-2017294410-A1 · Oct 12, 2017 · US
Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US-2017207206-A1 · Jul 20, 2017 · US
Integrated electronic package and stacked assembly thereof
US-9698104-B2 · Jul 4, 2017 · US
Stub minimization for assemblies without wirebonds to package substrate
US-9679838-B2 · Jun 13, 2017 · US
Selectively recessed reference plane structure in module tab area of memory module and method for forming selectively recessed reference plane
US-9618983-B2 · Apr 11, 2017 · US
Wafer-level flipped die stacks with leadframes or metal foil interconnects
US-2017077016-A1 · Mar 16, 2017 · US
Microelectronic packages and assemblies with improved flyby signaling operation
US-9595511-B1 · Mar 14, 2017 · US
Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
US-9595485-B2 · Mar 14, 2017 · US
Laminated interposers and packages with embedded trace interconnects
US-2016379967-A1 · Dec 29, 2016 · US
Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US-9524950-B2 · Dec 20, 2016 · US
Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US-2016358831-A1 · Dec 8, 2016 · US
Three-dimensional one-time-programmable memory comprising off-die read/write-voltage generator
US-9508395-B2 · Nov 29, 2016 · US
Package structure and method for fabricating the same
US-9502335-B2 · Nov 22, 2016 · US
Wafer-level flipped die stacks with leadframes or metal foil interconnects
US-9490195-B1 · Nov 8, 2016 · US
Semiconductor package including a plurality of chips
US-9490237-B2 · Nov 8, 2016 · US
Integrated electronic package and stacked assembly thereof
US-2016293551-A1 · Oct 6, 2016 · US
Three-Dimensional Vertical Memory Comprising Dice with Different Interconnect Levels
US-2016293584-A1 · Oct 6, 2016 · US
Stub minimization for assemblies without wirebonds to package substrate
US-2016268187-A1 · Sep 15, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W72/801?
- CPC H10W72/801 is the Cooperative Patent Classification code for “Interconnections on sidewalls of containers.”
- How many patents are filed under CPC H10W72/801 (Interconnections on sidewalls of containers)?
- Our database includes 184 publications tagged with this CPC code.
- Is patent activity under CPC H10W72/801 growing?
- Publication counts under this code: 17 in 2024 vs 14 in 2025 (latest complete years).