Integrated electronic package and stacked assembly thereof

Patent metadata

Field	Value
Publication number	US-2016293551-A1
Application number	US-201615182547-A
Country	US
Kind code	A1
Filing date	Jun 14, 2016
Priority date	Jul 1, 2014
Publication date	Oct 6, 2016
Grant date	—

Abstract

A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.

First claim

What is claimed is:

1 . An integrated electronic package comprising:
a platform segment having a cavity extending through said platform segment, said platform segment having a first surface and a second surface opposing said first surface, said platform segment comprising a semiconductor material; an electronic device residing in said cavity, said electronic device having an active side at which electrical contacts are located and a back side opposing said active side, wherein said active side is approximately coplanar with said first surface of said platform segment; and encapsulation material in said cavity, said encapsulation material coupling said electronic device to said platform segment, wherein said active side of said electronic device is exposed from said encapsulation material and said first and second surfaces of said platform segment are exposed from said encapsulation material.

2 . The integrated electronic package of claim 1 wherein said platform segment comprises a portion of a silicon crystal wafer.

3 . The integrated electronic package of claim 1 wherein said platform segment has a thickness that is greater than a height of said electronic device.

4 . The integrated electronic package of claim 3 wherein said back side of said electronic device residing in said cavity is embedded in said encapsulation material.

5 . The integrated electronic package of claim 1 further comprising a metallization layer formed directly on a non-cavity area of said platform segment.

6 . The integrated electronic package of claim 1 further comprising a conductive via extending through said platform segment at a non-cavity area of said platform segment.

7 . The integrated electronic package of claim 6 further comprising:
at least one insulating layer formed over said non-cavity area of said second surface of said platform segment;
an opening formed in said at least one insulating layer to expose said conductive via; and
a conductive interconnect extending through said opening in said at least one insulating layer and in electrical contact with said conductive via, said conductive interconnect extending over said non-cavity area of said platform segment.

8 . The integrated electronic package of claim 1 further comprising:
at least one insulating layer formed over said active side of said electronic device and over a non-cavity area of said platform segment;
an opening formed in said at least one insulating layer to expose one of said electrical contacts on said active side of said at least one electronic device; and
a conductive interconnect extending through said opening in said at least one insulating layer and extending over said non-cavity area of said platform segment.

9 . The integrated electronic package of claim 8 wherein said conductive interconnect extends to and is exposed at a side wall of said integrated electronic package.

10 . The integrated electronic package of claim 9 further comprising a conductive trace extending along said side wall, said conductive trace being in electrical communication with said conductive interconnect.

11 . A stacked assembly comprising the integrated electronic package of claim 10 and a second integrated electronic package bonded with said integrated electronic package, said second integrated electronic package having a second conductive interconnect in electrical communication with said conductive trace.

12 . The integrated electronic package of claim 1 wherein said electronic device is a first electronic device, and said integrated electronic package further comprises a second electronic device residing in said cavity and laterally displaced from said first electronic device, said second electronic device having a second active side at which second electrical contacts are located, wherein said second active side is approximately coplanar with said first surface of said platform segment, and said encapsulation material couples said second electronic device to said platform segment with said second active side being exposed from said encapsulation material.

13 . An integrated electronic package comprising:
a platform segment having a cavity extending through said platform segment, said platform segment having a first surface and a second surface opposing said first surface, said platform segment comprising a portion of a silicon crystal wafer; an electronic device residing in said cavity, said electronic device having an active side at which electrical contacts are located and a back side opposing said active side, wherein said active side is approximately coplanar with said first surface of said platform segment; a conductive via extending through said platform segment at a non-cavity area of said platform segment; and encapsulation material in said cavity, said encapsulation material coupling said electronic device to said platform segment, wherein said active side of said electronic device is exposed from said encapsulation material and said first and second surfaces of said platform segment are exposed from said encapsulation material.

14 . The integrated electronic package of claim 13 wherein said platform segment has a thickness that is greater than a height of said electronic device residing in said cavity, and said back side of said electronic device is embedded in said encapsulation material.

15 . The integrated electronic package of claim 13 further comprising a metallization layer formed directly on at least one of said first and second surfaces of said platform segment at a non-cavity area of said platform segment.

16 . The integrated electronic package of claim 13 further comprising:
at least one insulating layer formed over said non-cavity area of at least one of said first and second surfaces of said platform segment;
an opening formed in said at least one insulating layer to expose said conductive via; and
a conductive interconnect extending through said opening in said at least one insulating layer and in electrical contact with said conductive via, said conductive interconnect extending over said non-cavity area of said platform segment.

17 . A stacked assembly comprising:
a first integrated electronic package including:
a platform segment having a cavity extending through said platform segment, said platform segment having a first surface and a second surface opposing said first surface, said platform segment comprising a semiconductor material;
a first electronic device residing in said cavity, said electronic device having an active side at which electrical contacts are located and a back side opposing said active side, wherein said active side is approximately coplanar with said first surface of said platform segment;
encapsulation material in said cavity, said encapsulation material coupling said electronic device to said platform segment, wherein said active side of said electronic device is exposed from said encapsulation material and said first and second surfaces of said platform segment are exposed from said encapsulation material;
at least one insulating layer formed over said active side of said first electronic device and over a non-cavity area of said platform segment;
an opening formed in said at least one insulating layer to expose one of said electrical contacts on said active side of said at least one electronic device; and
a first conductive interconnect extending through said opening in said at least one insulating layer and extending over said non-cavity area of said platform segment, wherein said first conductive interconnect extends to a

Assignees

• Freescale Semiconductor Inc

Inventors

• Yap Weng F
• Vincent Michael B

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/801

  Interconnections on sidewalls of containers · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title