Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices

Patent metadata

Field	Value
Publication number	US-2016358831-A1
Application number	US-201615144699-A
Country	US
Kind code	A1
Filing date	May 2, 2016
Priority date	Feb 28, 2006
Publication date	Dec 8, 2016
Grant date	—

Abstract

Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

First claim

1 - 10 . (canceled)

11 . A set of stacked microelectronic devices, comprising:
a first known good packaged microelectronic device including—
a first interposer substrate having a first side, a second side opposite the first side, a plurality of first interposer contacts at the first side, and a plurality of first interposer pads at the second side arranged in an array corresponding to a standard JEDEC pinout;
a first microelectronic die attached to the first side of the interposer substrate and electrically coupled to the first interposer contacts;
a plurality of first interconnects electrically coupled to and in contact with corresponding first interposer contacts; and
a first casing that encapsulates the first die, at least a portion of the first interposer substrate, and at least a portion of the first interconnects, wherein the first casing has a first thickness and each of the first interconnects has a thickness equal to or greater than the first thickness such that at least a portion of each first interconnect is accessible at a top surface of the first casing; and
a second known good packaged microelectronic device coupled to the first device in a stacked configuration, the second device including—
a second interposer substrate having a first side, a second side opposite the first side and facing the first microelectronic device, a plurality of second interposer contacts at the first side, and a plurality of second interposer pads arranged in an array at the second side, wherein the first interconnects are directly electrically coupled to corresponding second interposer pads;
a second microelectronic die carried by the first side of the second interposer substrate and electrically coupled to corresponding second interposer contacts;
a plurality of second interconnects electrically coupled to and in contact with corresponding second interposer contacts; and
a second casing that encapsulates the second die, at least a portion of the second interposer substrate, and at least a portion of the second interconnects.

12 . The stacked microelectronic devices of claim 11 wherein:
the first interconnects comprise a plurality of first conductive lead fingers attached to the first side of the first interposer substrate and projecting inwardly from a periphery of the first casing toward the first die, the first lead fingers being in contact with and electrically coupled to corresponding first interposer contacts; and
the second interconnects comprise a plurality of second conductive lead fingers attached to the first side of the second interposer substrate and projecting inwardly from a periphery of the second casing toward the second die, the second lead fingers being in contact with and electrically coupled to corresponding second interposer contacts.

13 . The stacked microelectronic devices of claim 12 wherein the first and second lead fingers each include:
a front portion facing toward the corresponding first or second die; and
a back portion opposite the front portion and generally aligned with the periphery of the corresponding first or second casing such that at least a portion of the lead finger is accessible at the periphery of each casing.

14 . The stacked microelectronic devices of claim 12 , further comprising a plurality of electrical connectors coupling the exposed portion of each of the first lead fingers at the top surface of the first casing to corresponding second interposer pads at the second side of the second interposer substrate.

15 . The stacked microelectronic devices of claim 12 wherein:
the first interconnects comprise a plurality of first filaments attached to and projecting away from corresponding first interposer contacts; and
the second interconnects comprise a plurality of second filaments attached to and projecting away from corresponding second interposer contacts.

16 . The stacked microelectronic devices of claim 15 wherein:
the first filaments include a plurality of first free-standing wire-bond lines attached to corresponding first interposer contacts; and
the second flexible interconnects include a plurality of second free-standing wire-bond lines attached to corresponding second interposer contacts.

17 . The stacked microelectronic devices of claim 15 , further comprising a plurality of electrical couplers attached to a distal portion of each of the first and second filaments, and wherein the electrical couplers on the first filaments are electrically coupled to corresponding second interposer pads.

18 . The stacked microelectronic devices of claim 15 wherein:
the first interconnects include a plurality of first wire loops attached to corresponding first interposer contacts; and
the second interconnects include a plurality of second wire loops attached to corresponding second interposer contacts.

19 - 23 . (canceled)

24 . The stacked microelectronic devices of claim 11 wherein:
the first die includes an active side, a back side adjacent to the first side of the first interposer substrate, a plurality of first terminals at the active side, and integrated circuitry electrically coupled to the first terminals, and wherein the first terminals are electrically coupled to corresponding first interposer contacts with a plurality of first wire-bonds; and
the second die includes an active side, a back side adjacent to the first side of the second interposer substrate, a plurality of second terminals at the active side, and integrated circuitry electrically coupled to the second terminals, and wherein the second terminals are electrically coupled to corresponding second interposer contacts with a plurality of second wire-bonds.

25 . The stacked microelectronic devices of claim 11 wherein:
the first die includes an active side adjacent to the first side of the first interposer substrate, a back side, a plurality of first terminals at the active side, and integrated circuitry electrically coupled to the first terminals, and wherein the first terminals are electrically coupled to corresponding first interposer contacts; and
the second die includes an active side adjacent to the first side of the second interposer substrate, a back side, a plurality of second terminals at the active side, and integrated circuitry electrically coupled to the second terminals, and wherein the second terminals are electrically coupled to corresponding second interposer contacts.

26 . The stacked microelectronic devices of claim 11 , further comprising a plurality of electrical couplers attached to corresponding first interposer pads.

27 . The stacked microelectronic devices of claim 11 , further comprising an underfill material between the first and second devices.

28 . The stacked microelectronic devices of claim 11 wherein the second casing has a second thickness and each of the second interconnects has a thickness equal to or greater than the second thickness such that at least a portion of each second interconnect is accessible at a top surface of the second casing, and wherein the assembly further comprises:
a third microelectronic device coupled to the second device in a stacked configuration, the third device including—
a third interposer substrate having a plurality of third interposer pads, wherein the third interposer pads are electrically coupled to the exposed portions of corresponding second interconnects at the top surface of the second casing;
a third microelectronic die carried by and electrically coupled to the third interposer substrate; and
a third casing that encapsulates the third die and at least a portion of the third interposer substrate.

Assignees

• Micron Technology Inc

Inventors

• Corisis David J
• Chong Chin Hui
• Lee Choon Kuan

Classifications

• H10P74/20

  characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title