Three-Dimensional Vertical Memory Comprising Dice with Different Interconnect Levels

Patent metadata

Field	Value
Publication number	US-2016293584-A1
Application number	US-201615185004-A
Country	US
Kind code	A1
Filing date	Jun 16, 2016
Priority date	Sep 1, 2011
Publication date	Oct 6, 2016
Grant date	—

Abstract

The present invention discloses a three-dimensional vertical memory (3D-M V ). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. The number of interconnect levels in the peripheral-circuit die is more than the number of interconnect levels in the 3D-array die, but substantially less than the number of memory cells on each of the vertical memory strings in the 3D-array die.

First claim

What is claimed is:

1 . A three-dimensional vertical memory (3D-M V ), comprising:
a 3D-array die comprising at least a 3D-M V array, wherein said 3D-M V array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells; a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-M V array, wherein said off-die peripheral-circuit component is absent from said 3D-array die; means for coupling said 3D-array die and said peripheral-circuit die; wherein the number of interconnect levels in said peripheral-circuit die is more than the number of interconnect levels in said 3D-array die, but substantially less than the number of memory cells on each of said vertical memory strings in said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.

2 . The memory according to claim 1 , wherein said 3D-M V is a vertical-NAND.

3 . The memory according to claim 1 , wherein said 3D-M V is a three-dimensional read-only memory (3D-ROM).

4 . The memory according to claim 1 , wherein said 3D-M V is a vertical-NAND, a three-dimensional random-access memory (3D-RAM).

5 . The memory according to claim 1 , wherein said 3D-M V is a 3D-memristor.

6 . The memory according to claim 1 , wherein said 3D-M V is a 3D-RRAM or 3D-ReRAM (resistive random-access memory).

7 . The memory according to claim 1 , wherein said 3D-M V is a 3D-PCM (phase-change memory).

8 . The memory according to claim 1 , wherein said 3D-M V is a 3D-PMC (programmable metallization-cell memory).

9 . The memory according to claim 1 , wherein said 3D-M V is a 3D-CBRAM (conductive-bridging random-access memory).

10 . The memory according to claim 1 , wherein said 3D-array die and said peripheral-circuit die are located in a memory package.

11 . The memory according to claim 1 , wherein said 3D-array die and said peripheral-circuit die are located in a memory module.

12 . The memory according to claim 1 , wherein said 3D-array die and said peripheral-circuit die are located in a memory card.

13 . The memory according to claim 1 , wherein said 3D-array die and said peripheral-circuit die are located in a solid-state drive.

14 . The memory according to claim 1 , further comprising another 3D-array die including at least another 3D-M V array, wherein said peripheral-circuit die comprises at least another portion of another off-die peripheral-circuit component for said another 3D-array die.

15 . The memory according to claim 1 , wherein said off-die peripheral-circuit component is a read-voltage generator.

16 . The memory according to claim 1 , wherein said off-die peripheral-circuit component is a write-voltage generator.

17 . The memory according to claim 1 , wherein said off-die peripheral-circuit component is an address translator.

18 . The memory according to claim 1 , wherein said off-die peripheral-circuit component is a data translator.

Assignees

• Zhang Guobiao
• Hangzhou Haicun Information Tech Co Ltd

Inventors

• Zhang Guobiao

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C13/0011

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title

• G11C5/145

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title