Wafer-level flipped die stacks with leadframes or metal foil interconnects

Patent metadata

Field	Value
Publication number	US-9490195-B1
Application number	US-201514883864-A
Country	US
Kind code	B1
Filing date	Oct 15, 2015
Priority date	Jul 17, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.

First claim

The invention claimed is:

1. A stacked microelectronic assembly, comprising:
a plurality of stacked encapsulated microelectronic packages, each encapsulated microelectronic package comprising:
a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane of the front surface, the microelectronic element having a plurality of chip contacts at the front surface;
an encapsulation region having a major surface substantially parallel to the plane of the microelectronic element and a plurality of remote surfaces extending away from the major surface, and the encapsulation region extending from at least one edge surface of the microelectronic element to at least one of the remote surfaces which overlies the edge surface; and
a plurality of electrically conductive package contacts at a single one of the remote surfaces spaced apart from the corresponding adjacent edge surface of the microelectronic element of the package, the chip contacts electrically coupled with the package contacts,

the plurality of microelectronic packages stacked one above another in the stacked assembly such that the planes of the microelectronic elements are parallel to one another, and the major surfaces of the encapsulation regions of respective microelectronic packages in the stacked assembly are oriented towards one another,
wherein the package contacts are configured for electrically connecting the microelectronic assembly with a corresponding set of substrate contacts at a major surface of a substrate in a state in which the major surface of the substrate is oriented at a substantial angle to the plane of each microelectronic element and is oriented towards each single remote surface of each of the stacked microelectronic packages.

2. The stacked microelectronic assembly as claimed in claim 1 , wherein the plurality of package contacts of each package in the stacked assembly are electrically coupled with the corresponding set of substrate contacts at the major surface of the substrate.

3. The stacked microelectronic assembly as claimed in claim 2 , wherein a package of the stacked microelectronic packages includes a plurality of the microelectronic elements stacked such that the planes of the stacked microelectronic elements of such package are parallel to one another, wherein the encapsulation region of the package is in contact with the edge surfaces of each of the stacked microelectronic elements of the package, and the chip contacts of each of the stacked microelectronic elements of the package are electrically coupled with the package contacts of the at package.

4. The stacked microelectronic assembly as claimed in claim 1 , wherein the encapsulation region of each package contacts at least two of the edge surfaces of the microelectronic element of the package, such that at least two of the remote surfaces of the package are defined by surfaces of the encapsulation region which are spaced apart from the corresponding adjacent edge surfaces.

5. The stacked microelectronic assembly as claimed in claim 1 , wherein ends of the package contacts coupled to the microelectronic element of each package extend beyond the remote surface of the encapsulation region of such package.

6. The microelectronic assembly as claimed in claim 1 , wherein the package contacts comprise leadframe interconnects, the leadframe interconnects electrically coupled with the chip contacts of the package through leads.

7. The microelectronic assembly as claimed in claim 6 , wherein ends of the leadframe interconnects coupled to the microelectronic element in a respective one of the microelectronic packages are flush with or recessed relative to the remote surface of the encapsulation region of such package.

8. A stacked microelectronic assembly, comprising:
a plurality of stacked encapsulated microelectronic packages, each encapsulated microelectronic package comprising:
a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane of the front surface, the microelectronic element having a plurality of chip contacts at the front surface;
an encapsulation region having a major surface substantially parallel to the plane of the microelectronic element and a plurality of remote surfaces extending away from the major surface, the encapsulation region extending from at least one edge surface of the microelectronic element to at least one of the remote surfaces which overlies the edge surface; and
a plurality of electrically conductive package contacts at a single one of the remote surfaces spaced apart from the corresponding adjacent edge surface of the microelectronic element of the package, the chip contacts electrically coupled with the package contacts,

the plurality of microelectronic packages stacked one above another in the stacked assembly such that the planes of the microelectronic elements are parallel to one another, and the major surfaces of the encapsulation regions of respective microelectronic packages in the stacked assembly are oriented towards one another,
wherein the major surfaces of the encapsulation regions of at least two adjacent microelectronic packages in the stacked assembly are separated from one another by a gap of at least 100 microns, further comprising a heat spreader having at least a portion disposed between the encapsulation regions of the at least two adjacent microelectronic packages in the stacked assembly.

9. The stacked microelectronic assembly as claimed in claim 8 , further comprising an adhesive contacting the remote surfaces of each package at which the package contacts are disposed, the major surface of the substrate, and the adhesive surrounding each of the connections between the package contacts and the substrate contacts, wherein features at the major surface of the substrate aligned with the gap define flow paths configured to convey the adhesive across the gap.

10. A microelectronic package, comprising:
a plurality of stacked microelectronic elements each microelectronic element having a front surface defining a plane extending in a first direction and a second direction transverse to the first direction, a plurality of edge surfaces extending away from the plane of the front surface, each microelectronic element having a plurality of chip contacts at the front surface, the microelectronic elements stacked with the planes parallel to one another;
an encapsulation region having a major surface substantially parallel to the plane of each stacked microelectronic element and having a plurality of remote surfaces extending away from the major surface, the encapsulation region extending from at least one edge surface of the microelectronic element to at least one of the remote surfaces which overlies the edge surface; and
a plurality of electrically conductive package contacts disposed at a single one of the remote surfaces, the chip contacts of each of the stacked microelectronic elements electrically coupled with the package contacts,
wherein the package contacts are configured for electrically connecting the microelectronic package with a corresponding set of substrate contacts at a major surface of a substrate in a state in which the major surface of the substrate is oriented at a substantial angle to the plane of the microelectronic element and is oriented towards the single one of the remote surfaces of the microelectronic package.

11. The microelectronic package as claimed in claim 10 , wherein the package contacts comprise leadframe interconnects, the leadframe interconnects electrically coupled with the chip contacts through leads coupled to the leadframe interconnects.

Assignees

• Invensas Corp

Inventors

• Prabhu Ashok S
• Katkar Rajesh
• Moran Sean

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title