Stub minimization for assemblies without wirebonds to package substrate

Patent metadata

Field	Value
Publication number	US-2016268187-A1
Application number	US-201615165323-A
Country	US
Kind code	A1
Filing date	May 26, 2016
Priority date	Oct 3, 2011
Publication date	Sep 15, 2016
Grant date	—

Abstract

A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

First claim

1 . A microelectronic package, comprising:
a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function, the microelectronic element having one or more columns of element contacts each column extending in a first direction along a face of the microelectronic element, such that an axial plane extending in a direction normal to the face of the microelectronic element intersects the face of the microelectronic element along a line extending in the first direction and centered relative to the one or more columns of element contacts; packaging structure including: a dielectric layer having a surface overlying the face of the microelectronic element and facing away from the face of the microelectronic element, and a plurality of terminals exposed at the surface of the dielectric layer, at least some of the terminals being electrically connected with the element contacts through traces extending along the dielectric layer and metallized vias extending from the traces and contacting the element contacts, the terminals disposed at positions within a plurality of parallel columns and being configured for connecting the microelectronic package to at least one component external to the microelectronic package, the terminals including first terminals disposed within at least one column in the central region, the first terminals being configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element, wherein the central region is not wider than three and one-half times a minimum pitch between any two adjacent columns of the terminals, and the axial plane intersects the central region.

Assignees

• Invensas Corp

Inventors

• Crisp Richard Dewitt
• Zohni Wael
• Haba Belgacem
• Lambrecht Frank

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/801

  Interconnections on sidewalls of containers · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title