Packaged semiconductor device and method of fabricating a packaged semiconductor device

Patent metadata

Field	Value
Publication number	US-2017373016-A1
Application number	US-201615235114-A
Country	US
Kind code	A1
Filing date	Aug 12, 2016
Priority date	Jun 28, 2016
Publication date	Dec 28, 2017
Grant date	—

Abstract

In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive bump, a second package structure, a sealing material, and an electromagnetic interference (EMI) shielding layer. The first package structure has a first cut edge. The outer conductive bump is disposed on the first package structure and has a second cut edge. The second package structure is jointed onto the first package structure. The sealing material is disposed on the first package structure, surrounds the second package structure, and covers the outer conductive bump. The sealing material has a third cut edge. The EMI shielding layer contacts the first cut edge, the second cut edge and the third cut edge. The EMI shielding layer is electrically connected with the outer conductive bump.

First claim

What is claimed is:

1 . A packaged semiconductor device, comprising:
a first package structure having a first cut edge; at least one outer conductive bump disposed on the first package structure and having a second cut edge; a second package structure jointed onto the first package structure; a sealing material disposed on the first package structure, surrounding the second package structure, and covering the outer conductive bump, wherein the sealing material has a third cut edge; and an electromagnetic interference (EMI) shielding layer disposed over the first cut edge, the second cut edge, and the third cut edge, and being in electrical contact with the outer conductive bump.

2 . The packaged semiconductor device as claimed in claim 1 , wherein the first cut edge, the second cut edge and the third cut edge than a side edge and the EMI shielding layer cover the side edge in a conformal manner.

3 . The packaged semiconductor device as claimed in claim 1 , wherein the first package structure comprises a die, a molding compound and at least one outer via, the die and the outer via are encapsulated by the molding compound, the outer via penetrates the molding compound, and the EMI shielding layer is electrically connected with the outer via through the outer conductive bump.

4 . The packaged semiconductor device as claimed in claim 3 , wherein an outer edge of the outer via is covered by the molding compound and spaced from the first cut edge by a distance.

5 . The packaged semiconductor device as claimed in claim 3 , wherein a width of the outer conductive bump is greater than a contact width of the outer conductive bump contacting the outer via.

6 . The packaged semiconductor device as claimed in claim 3 , further comprising a plurality of inter-conductive bumps connected between the first package structure and the second package structure, wherein the inter-conductive bumps are surrounded by the sealing material.

7 . The packaged semiconductor device as claimed in claim 6 , wherein the outer conductive via is connected to the outer conductive bump and one of the inter-conductive bumps.

8 . The packaged semiconductor device as claimed in claim 1 , further comprising a plurality of bottom conductive bumps disposed on the first package structure and exposed at a bottom of the packaged semiconductor structure.

9 . A packaged semiconductor device, comprising:
a first package structure comprising a die, a molding compound and at least one outer via, the die and the outer via being encapsulated by the molding compound, and the outer via penetrating through the molding compound; at least one outer conductive bump disposed on the first package structure and connected to the outer via; a second package structure, jointed onto the first package structure; a sealing material being disposed on the first package structure, surrounding the second package structure, and covering the outer conductive bump; and an electromagnetic interference (EMI) shielding layer contacting the sealing material, the first package structure, and the outer conductive bump,
wherein the outer conductive bump mediates between the EMI shielding layer and the outer via and electrically connects the EMI shielding layer with the outer via.

10 . The packaged semiconductor device as claimed in claim 9 , wherein an outer edge of the outer via is covered by the molding compound and spaced from the EMI shielding layer by a distance.

11 . The packaged semiconductor device as claimed in claim 9 , wherein a width of the outer conductive bump is greater than a contact width of the outer conductive bump contacting the outer via.

12 . The packaged semiconductor device as claimed in claim 9 , further comprising a plurality of bottom conductive bumps disposed on the first package structure and exposed at a bottom of the packaged semiconductor structure.

13 . The packaged semiconductor device as claimed in claim 9 , further comprising a plurality of inter-conductive bumps connected between the first package structure and the second package structure, wherein the inter-conductive bumps are surrounded by the sealing material.

14 . The packaged semiconductor device as claimed in claim 13 , wherein the outer via is connected to one of the inter-conductive bumps and the outer conductive bumps.

15 . A method of fabricating a packaged semiconductor device, comprising:
forming a plurality of outer conductive bumps respectively on a plurality of first package structures encapsulated by a molding compound, wherein one outer conductive bump on one first package structure is spaced from another outer conductive bump on an adjacent first package structure by a distance; jointing a plurality of second package structures onto the first package structures and the second package structures exposing the outer conductive bumps; sealing the second package structures on the first package structure by using a sealing material; and performing a singulation process by cutting through the sealing material, the outer conductive bumps, and the molding compound to form a plurality of package on package devices, the outer conductive bumps being exposed at side edges of the package on package devices.

16 . The method as claimed in claim 15 , further comprising forming an EMI shielding layer on one of the package on package devices, wherein the EMI shielding layer is in contact with the outer conductive bump of the package on package device.

17 . The method as claimed in claim 15 , wherein the singulation process is performed by cutting the sealing material and the molding compound along a cutting trajectory extended along where the distance exists.

18 . The method as claimed in claim 15 , wherein the second package structures are respectively jointed onto the first package structures in a flip chip technique.

19 . The method as claimed in claim 15 , further comprising forming a plurality of bottom conductive bumps on the first package structures and the bottom conductive bumps are exposed at bottoms of the package on package devices.

20 . The method as claimed in claim 15 , wherein the package on package devices respectively have a first cut edge of the first package structure, a second cut edge of the outer conductive bump and a third cut edge of the sealing material after the singulation process and the first cut edge exposes the molding compound.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Cheng Li-Hui
• Tsai Po-Hao

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/801

  Interconnections on sidewalls of containers · CPC title

• H10W72/0198

  batch processes · CPC title