Semiconductor package including a plurality of chips

Patent metadata

Field	Value
Publication number	US-9490237-B2
Application number	US-201514593773-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Mar 8, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.

First claim

What is claimed is:

1. A semiconductor integrated device, comprising:
a plurality of electronic components, each of which including an I/O electrode;
an interconnection electrode unit formed on the I/O electrode of each of the electronic components;
a first insulating portion arranged on side surfaces of each of the electronic components, side surfaces of the interconnection electrode unit and a backside surface of each of the electronic components;
a second insulating portion formed on the first insulating portion and the interconnection electrode unit, the second insulating portion including a via on the interconnection electrode unit;
and a redistribution layer formed on the second insulating portion, the redistribution layer interconnected to the interconnection electrode unit,
wherein upper surfaces of the interconnection electrode unit and the first insulating portion are located on a substantially identical plane,
the redistribution layer electrically connects an interconnection electrode unit of at least one of the plurality of electronic components and an interconnection electrode unit of another one of the plurality of electronic components, and
the first insulating portion includes a first resin portion and a second resin portion, the first resin portion coats the side surfaces of each of the electronic components and the side surfaces of the interconnection electrode unit, and the second resin portion coats side surfaces or the side surfaces and a backside surface of the first resin portion.

2. The device according to claim 1 , wherein the first resin portion coats the backside surface of each of the electronic components.

3. The device according to claim 1 , wherein the interconnection electrode unit is a ball electrode.

4. The device according to claim 1 , wherein at least one of the electronic components is a semiconductor chip.

5. The device according to claim 1 , wherein at least one of the electronic components is a passive component.

Assignees

• Toshiba Kk

Inventors

• Yamada Hiroshi
• Onozuka Yutaka
• Iida Atsuko
• Itaya Kazuhiko

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title