Stub minimization for assemblies without wirebonds to package substrate

Patent metadata

Field	Value
Publication number	US-9679838-B2
Application number	US-201615165323-A
Country	US
Kind code	B2
Filing date	May 26, 2016
Priority date	Oct 3, 2011
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

First claim

The invention claimed is:

1. A microelectronic package, comprising:
first and second microelectronic elements each having memory storage array function, each microelectronic element having one or more columns of element contacts, each column of element contacts extending in a first direction along a face of such microelectronic element;
a substrate having first and second opposed surfaces and first and second opposed edges extending between the first and second surfaces, the first surface having first substrate contacts and second substrate contacts thereon, the first substrate contacts facing the element contacts of the first microelectronic element and joined thereto, and the second substrate contacts facing the element contacts of the second microelectronic element and joined thereto; and
a plurality of terminals exposed at the second surface of the substrate and electrically connected with the first and second substrate contacts, the terminals being disposed at positions within a plurality of columns extending along the second surface of the substrate and being configured to connect the microelectronic package to at least one component external to the microelectronic package,
the terminals including first and second duplicate sets of data terminals, the columns of the first and second duplicate sets of data terminals each extending in the first direction, wherein signal assignments of the first and second duplicate sets of data terminals are symmetric about an axis of symmetry extending in the first direction,
the terminals further including other terminals disposed between the first and second duplicate sets of data terminals that are configured to carry signals other than the signals carried by the data terminals.

2. The microelectronic package as claimed in claim 1 , wherein the other terminals disposed between the first and second duplicate sets of data terminals are configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the first and second microelectronic elements.

3. The microelectronic package as claimed in claim 2 , wherein the other terminals disposed between the first and second duplicate sets of data terminals are configured to carry all of the address information usable by the circuitry within the microelectronic package to determine the addressable memory location.

4. The microelectronic assembly as claimed in claim 2 , wherein the other terminals disposed between the first and second duplicate sets of data terminals are configured to carry all of the command signals transferred to the microelectronic package, the command signals being write enable, row address strobe, and column address strobe signals.

5. The microelectronic package as claimed in claim 2 , further comprising a buffer chip having a surface facing the first surface of the substrate, the buffer chip being electrically connected with the other terminals, the buffer chip being configured to regenerate at least some of the address information received at the other terminals and to output the regenerated address information to the first and second microelectronic elements.

6. The microelectronic package as claimed in claim 1 , wherein the terminals further include a third set of data terminals, the columns of the third set of data terminals each extending in a second direction.

7. The microelectronic package as claimed in claim 6 , wherein signal assignments of the third set of data terminals have modulo-X symmetry about the axis of symmetry, wherein X is an integer.

8. The microelectronic package as claimed in claim 7 , wherein X is equal to 2 raised to the power of n, n being greater than or equal to 2.

9. The microelectronic package as claimed in claim 7 , wherein X is equal to N times 8, wherein N is a whole number greater than or equal to one.

10. The microelectronic package as claimed in claim 7 , wherein X is greater than two.

11. The microelectronic package as claimed in claim 6 , wherein the terminals further include a fourth set of data terminals, the columns of the fourth set of data terminals each extending in the second direction, the third and fourth sets of data terminals being duplicate sets of the data terminals.

12. The microelectronic package as claimed in claim 11 , wherein signal assignments of the third and fourth duplicate sets of data terminals are symmetric about a second axis of symmetry extending in the second direction.

13. The microelectronic package as claimed in claim 11 , wherein the first and second duplicate sets of data terminals separate the third and fourth duplicate sets of data terminals from one another.

14. The microelectronic package as claimed in claim 1 , wherein the axis of symmetry is located within one ball pitch of the terminals of a centerline of the substrate located equidistant between the first and second opposed edges.

15. The microelectronic package as claimed in claim 1 , wherein each of the first and second microelectronic elements embody a greater number of active devices to provide memory storage array function than any other function.

16. The microelectronic package as claimed in claim 1 , wherein the memory storage array function of each of the first and second microelectronic elements is implemented in NAND flash, resistive RAM, phase-change memory, magnetic RAM, static RAM, dynamic RAM, spin-torque RAM, or content-addressable memory technology.

17. The microelectronic package as claimed in claim 1 , wherein each of the first and second microelectronic elements include a first semiconductor chip having contacts thereon joined to the substrate contacts and at least one second semiconductor chip overlying a face of the first semiconductor chip remote from the first surface of the substrate and electrically interconnected with the first semiconductor chip.

18. The microelectronic package as claimed in claim 1 , wherein the element contacts of each of the first and second microelectronic elements include redistribution contacts exposed at the face of the respective microelectronic element, each redistribution contact being electrically connected with a contact pad of the respective microelectronic element through at least one of a trace or a via, at least some of the redistribution contacts of each of the first and second microelectronic elements being displaced from the element contacts of the respective microelectronic element in at least one direction along the face of the respective microelectronic element.

19. A system comprising a microelectronic package according to claim 1 and one or more other electronic components electrically connected to the microelectronic package.

20. The system as claimed in claim 19 , further comprising a housing, the microelectronic package and the one or more other electronic components being assembled with the housing.

Assignees

• Invensas Corp

Inventors

• Crisp Richard Dewitt
• Zohni Wael
• Haba Belgacem
• Lambrecht Frank

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/801

  Interconnections on sidewalls of containers · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title