Selectively recessed reference plane structure in module tab area of memory module and method for forming selectively recessed reference plane

Patent metadata

Field	Value
Publication number	US-9618983-B2
Application number	US-201514625837-A
Country	US
Kind code	B2
Filing date	Feb 19, 2015
Priority date	Feb 25, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A memory module includes a signal tab and a power tab spaced apart from each other on a surface layer of a substrate, the signal tab and the power tab defining a module tab area, a reference plane layer below the surface layer, the reference plane layer being recessed below the signal tab and being non-recessed below the power tab, and an insulating layer between the surface layer and the reference plane layer.

First claim

What is claimed is:

1. A memory module, comprising:
a surface layer on a substrate, a portion of the surface layer including a signal tab and a power tab spaced apart from each other and defining a module tab area in the surface layer;
a reference plane layer below the surface layer, the reference plane layer being recessed below the signal tab and being non-recessed below the power tab; and
an insulating layer between the surface layer and the reference plane layer, the insulating layer being parallel to the substrate and separating the module tab area of the surface layer from the reference plane layer.

2. The memory module as claimed in claim 1 , wherein the power tab is a tab applied with a power supply voltage.

3. The memory module as claimed in claim 1 , wherein the power tab is a tab applied with a ground voltage.

4. The memory module as claimed in claim 1 , wherein the surface layer and the reference plane layer include a same conductive metal.

5. The memory module as claimed in claim 4 , wherein the conductive metal is a copper or a copper-based alloy.

6. The memory module as claimed in claim 1 , wherein the insulating layer completely separates the surface layer from the reference plane layer, the insulating layer being a prepreg layer.

7. The memory module as claimed in claim 1 , wherein:
the surface layer includes a first surface layer disposed at an uppermost portion of the substrate, and a second surface layer disposed at a lowermost portion of the substrate, and
the reference plane layer includes a first reference plane layer disposed below the first surface layer, and a second reference plane layer above the second surface layer.

8. The memory module as claimed in claim 1 , wherein the reference plane layer, the insulating layer, and the surface layer are stacked on the substrate in the stated order, only an edge of the reference plane layer overlapping the module tab area including a recessed portion below the signal tab.

9. The memory module as claimed in claim 1 , wherein the memory module is a dual in-line memory module (DIMM).

10. The memory module as claimed in claim 1 , wherein:
a non-recessed portion of the reference plane layer is a layer portion overlapping the power tab, and
a recessed portion of the reference plane layer is an empty space overlapping the signal tab, the empty space directly contacting a lateral side of the layer portion and having a same thickness as the layer portion along a direction normal to the substrate.

11. The memory module as claimed in claim 1 , wherein the reference plane layer is recessed only below the signal tab among the signal tab and the power tab.

12. A method for forming a selectively recessed reference plane, the method comprising:
forming a signal tab and a power tab spaced apart from each other on a surface layer of a substrate, the signal tab and the power tab defining a module tab area;
forming a reference plane layer below the surface layer, such that the reference plane layer is recessed below the signal tab and non-recessed below the power tab; and
forming an insulating layer between the surface layer and the reference plane layer, such that the insulating layer is parallel to the substrate and separates the module tab area of the surface layer from the reference plane layer.

13. The method as claimed in claim 12 , wherein the signal tabs are contact terminals for data communication between a semiconductor memory chip and an external controller.

14. The method as claimed in claim 12 , wherein the power tabs are contact terminals to apply a power supply voltage or a ground voltage to a semiconductor memory chip.

15. The method as claimed in claim 12 , wherein forming the signal tabs includes recessing via an etch process.

16. The method as claimed in claim 12 , wherein forming the signal tabs and the power tabs includes a same material as that of the reference plane layer.

17. A memory module, comprising:
a surface layer on a substrate, an edge of the surface layer defining at least one signal tab and at least one power tab spaced apart horizontally from each other;
a reference plane layer on the surface layer, the reference plane layer including:
a layer portion overlapping the at least one power tab, and
an empty space overlapping the at least one signal tab, the empty space directly contacting a lateral side of the layer portion and having a same thickness as the layer portion along a direction normal to the substrate; and

an insulating layer between the surface layer and the reference plane layer, the insulating layer covering the layer portion and the empty space.

18. The memory module as claimed in claim 17 , wherein the empty space overlaps only the signal tab among the at least one signal tab and the at least one power tab, the empty space completely overlapping the at least one signal tab, and the layer portion completely overlapping the at least one power tab.

19. The memory module as claimed in claim 18 , wherein the insulating layer completely and continuously overlapping the at least one power tab, the at least one signal tab, and a space between the power and signal tabs, the reference plane layer being electrically connected to the power tab through a via contact in the insulating layer.

20. The memory module as claimed in claim 17 , wherein the substrate is a multi-layered printed circuit board (PCB).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dongyeop
• Lee Jaejun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title