Three-dimensional one-time-programmable memory comprising off-die read/write-voltage generator

Patent metadata

Field	Value
Publication number	US-9508395-B2
Application number	US-201615062117-A
Country	US
Kind code	B2
Filing date	Mar 6, 2016
Priority date	Sep 1, 2011
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die read/write-voltage generator (V R /V W -generator). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a V R /V W -generator of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The V R /V W -generator generates at least a read voltage and/or a write voltage different from a supply voltage.

First claim

What is claimed is:

1. A discrete three-dimensional one-time-programmable memory (3D-OTP), comprising:
a 3D-array die comprising at least a 3D-OTP array, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells;
a peripheral-circuit die comprising at least an off-die V R /V W -generator of said 3D-OTP array, wherein said off-die V R /V W -generator generates at least a read voltage and/or a write voltage different from a supply voltage;
means for coupling said 3D-array die and said peripheral-circuit die;
wherein the number of back-end-of-line (BEOL) levels in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die; said off-die V R /V W -generator is absent from said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.

2. The memory according to claim 1 , wherein each of said 3D-OTP cells comprises an antifuse layer.

3. The memory according to claim 1 , wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card, or a solid-state drive.

4. The memory according to claim 1 , further comprising another 3D-array die including at least another 3D-OTP array, wherein said peripheral-circuit die comprises at least another portion of another off-die V R /V W -generator for said another 3D-array die.

5. The memory according to claim 1 , wherein said off-die V R /V W -generator is a read-voltage generator.

6. The memory according to claim 1 , wherein said off-die V R /V W -generator is a write-voltage generator.

7. A discrete three-dimensional one-time-programmable memory (3D-OTP), comprising:
a 3D-array die comprising at least a 3D-OTP array, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells;
a peripheral-circuit die comprising at least an off-die V R /V W -generator of said 3D-OTP array, wherein said off-die V R /V W -generator generates at least a read voltage and/or a write voltage different from a supply voltage;
means for coupling said 3D-array die and said peripheral-circuit die;
wherein the number of interconnect levels in said peripheral-circuit die is more than the number of interconnect levels in said 3D-array die, but substantially less than the number of back-end-of-line (BEOL) levels in said 3D-array die; said off-die V R /V W -generator is absent from said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.

8. The memory according to claim 7 , wherein each of said 3D-OTP cells comprises an antifuse layer.

9. The memory according to claim 7 , wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card, or a solid-state drive.

10. The memory according to claim 7 , further comprising another 3D-array die including at least another 3D-OTP array, wherein said peripheral-circuit die comprises at least another portion of another off-die peripheral-circuit component for said another 3D-array die.

11. The memory according to claim 7 , wherein said off-die V R /V W -generator is a read-voltage generator.

12. The memory according to claim 7 , wherein said off-die V R /V W --generator is a write-voltage generator.

13. A discrete three-dimensional one-time-programmable memory (3D-OTP), comprising:
a 3D-array die comprising at least a 3D-OTP array and an in-die peripheral-circuit component, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells;
a peripheral-circuit die comprising at least an off-die peripheral-circuit component including an off-die V R /V W -generator of said 3D-OTP array, wherein said off-die V R /V W -generator generates at least a read voltage and/or a write voltage different from a supply voltage;
means for coupling said 3D-array die and said peripheral-circuit die;
wherein said off-die peripheral-circuit component and said in-die peripheral-circuit component comprise different interconnect materials; said off-die V R /V W -generator is absent from said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.

14. The memory according to claim 13 , wherein said 3D-array die comprises high-temperature interconnect materials.

15. The memory according to claim 13 , wherein said peripheral-circuit die comprises high-speed interconnect materials.

16. The memory according to claim 13 , wherein each of said 3D-OTP cells comprises an antifuse layer.

17. The memory according to claim 13 , wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card, or a solid-state drive.

18. The memory according to claim 13 , further comprising another 3D-array die including at least another 3D-OTP array, wherein said peripheral-circuit die comprises at least another portion of another off-die V R /V W -generator for said another 3D-array die.

19. The memory according to claim 13 , wherein said off-die V R /V W -generator is a read-voltage generator.

20. The memory according to claim 13 , wherein said off-die V R /V W -generator is a write-voltage generator.

Assignees

• Hangzhou Haicun Information Tech Co Ltd

Inventors

• Zhang Guobiao

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title