Integrated circuit device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12288805-B2
Application number	US-202418667417-A
Country	US
Kind code	B2
Filing date	May 17, 2024
Priority date	Mar 10, 2021
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit device, the method comprising:
forming a structure including a fin-type active region, extending in a first horizontal direction on a substrate, and a channel region on the fin-type active region;
forming a dummy gate layer extending in a second horizontal direction crossing the first horizontal direction on the channel region;
forming an insulating spacer layer covering a sidewall of the dummy gate layer;
forming a sacrificial insulating layer conformally covering the insulating spacer layer;
forming a recess exposing the channel region on the fin-type active region by removing a portion of each of the sacrificial insulating layer and the insulating spacer layer, and forming an insulating spacer including a portion covering the sidewall of the dummy gate layer;
forming a source/drain region connected to the channel region in the recess and including a first portion facing the sidewall of the dummy gate layer with the sacrificial insulating layer and the insulating spacer therebetween;
forming a first space between the insulating spacer and the first portion of the source/drain region by removing the sacrificial insulating layer;
forming an insulating liner covering the insulating spacer and the source/drain region and defining an air gap including at least a portion of the first space;
forming a gate space on the channel region by removing the dummy gate layer; and
forming a gate line in the gate space.

2. The method of claim 1 , wherein, in the forming of the insulating liner, the insulating liner is formed such that a size of the air gap in the first horizontal direction is equal to a size of the first space.

3. The method of claim 1 , wherein, in the forming of the insulating liner, the insulating liner is formed such that a size of the air gap in the first horizontal direction is less than a size of the first space.

4. The method of claim 1 , wherein the insulating spacer includes a SiOCN layer, a SiON layer, or a combination thereof, and the sacrificial insulating layer includes a SiN layer.

5. The method of claim 1 , wherein, in the forming of the insulating liner, the insulating liner is formed using a material different from that of the insulating spacer.

6. The method of claim 1 , wherein the forming of the insulating spacer includes etching a portion of the insulating spacer layer while forming the recess to thereby form the insulating spacer, including a lower portion region adjacent to a bottom of the recess from the insulating spacer layer, and further including an upper portion region covering the sidewall of the dummy gate layer,
wherein, in the forming of the source/drain region, the source/drain region is formed to contact the lower portion region of the insulating spacer.

7. The method of claim 1 , wherein the source/drain region includes a Si layer doped with an n-type dopant.

8. The method of claim 1 , wherein the source/drain region includes a SiGe layer doped with a p-type dopant.

9. The method of claim 1 , wherein the forming of the structure includes forming, on the substrate, the fin-type active region and a multilayer in which a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers are alternately stacked one by one,
the forming of the recess and the insulating spacer comprises etching a portion of each of the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers in the multilayer to form a plurality of nanosheets constituting the channel region from the plurality of nanosheet semiconductor layers, and
the forming of the gate space comprises removing the plurality of sacrificial semiconductor layers remaining on the substrate after removing the dummy gate layer.

10. The method of claim 9 , further comprising:
after the forming of the recess and the insulating spacer and before the forming of the source/drain region, removing a portion of each of the plurality of sacrificial semiconductor layers remaining on the substrate through the recess to form a plurality of indent spaces; and
forming a plurality of inner insulating spacers filling the plurality of indent spaces.

11. A method of manufacturing an integrated circuit device, the method comprising:
forming a plurality of structures, each of the plurality of structures including a fin-type active region extending in a first horizontal direction on a substrate and further including a channel region on the fin-type active region, the substrate including a first device region and a second device region;
forming a dummy gate layer extending in a second horizontal direction crossing the first horizontal direction on the channel region in each of the first device region and the second device region;
forming an insulating spacer layer covering a sidewall of the dummy gate layer in each of the first device region and the second device region;
forming a first sacrificial insulating layer conformally covering the insulating spacer layer in each of the first device region and the second device region;
in a state in which the first device region is covered with a first mask pattern, forming a second region recess exposing the channel region on the fin-type active region by removing a portion of each of the first sacrificial insulating layer, the insulating spacer layer, and the fin-type active region in the second device region, and forming a second region insulating spacer covering the sidewall of the dummy gate layer in the second device region;
forming a first conductivity-type source/drain region connected to the channel region in the second region recess and including a first portion facing the sidewall of the dummy gate layer with the first sacrificial insulating layer and the second region insulating spacer therebetween in the second device region;
exposing the insulating spacer layer in the first device region and forming a first space between the first portion of the first conductivity-type source/drain region and the second region insulating spacer in the second device region by removing the first sacrificial insulating layer in each of the first device region and the second device region; and
forming an insulating liner conformally covering the second region insulating spacer and the first conductivity-type source/drain region in the second device region and defining a second region air gap including at least a portion of the first space.

12. The method of claim 11 , further comprising:
after the forming of the first space in the second device region and before the forming of the insulating liner:
forming a second sacrificial insulating layer covering the insulating spacer layer in the first device region and filling the first space in the second device region;
in a state in which the second device region is covered with a second mask pattern, forming a first region recess exposing the channel region on the fin-type active region by removing a portion of each of the second sacrificial insulating layer, the insulating spacer layer, and the fin-type active region in the first device region, and forming a first region insulating spacer covering the sidewall of the dummy gate layer in the first device region;
forming a second conductivity-type source/drain region connected to the channel region in the first region recess and including a second portion facing the sidewall of the dummy gate layer with a portion of the second sacrificial insulating layer and the first region insulating spacer therebetween in the first device region; and
forming a second space between the second portion of the second conductivity-type source/drain

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jinbum
• Kim Gyeom
• Kim Hyojin
• Yu Haejun
• Lee Seunghun
• Choi Kyungin

Classifications

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title