Air gap spacer integration for improved fin device performance

Patent metadata

Field	Value
Publication number	US-9515156-B2
Application number	US-201514884264-A
Country	US
Kind code	B2
Filing date	Oct 15, 2015
Priority date	Oct 17, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

First claim

What is claimed is:

1. A method for providing a FinFET device with an air gap spacer, comprising:
providing a substrate including a plurality of fins and a dummy gate arranged transverse to the plurality of fins;
depositing a sacrificial spacer around the dummy gate;
depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer;
selectively etching the dummy gate relative to the first ILD layer and the sacrificial spacer;
depositing a replacement metal gate (RMG);
etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and
depositing a gate capping layer in the recess, wherein the gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

2. The method of claim 1 , wherein the gate capping layer is deposited using a remote plasma process.

3. The method of claim 1 , wherein the sacrificial spacer is made of silicon nitride.

4. The method of claim 1 , further comprising performing chemical mechanical polishing (CMP) of the gate capping layer.

5. The method of claim 1 , further comprising:
etching the first ILD layer around opposite ends of the plurality of fins to create recesses for self-aligned contacts (SACs); and
depositing the SACs in the recesses.

6. The method of claim 5 , wherein the depositing the SACs in the recesses includes:
depositing a barrier layer; and
depositing a metal layer.

7. The method of claim 6 , wherein the barrier layer includes titanium and titanium nitride layers.

8. The method of claim 6 , wherein the barrier layer includes WCNx, where x is an integer greater than zero.

9. The method of claim 5 , wherein the SACs include a metal layer including a material selected from a group consisting of tungsten (W) and cobalt (Co).

10. The method of claim 5 , further comprising removing the sacrificial spacer by selectively etching the sacrificial spacer relative to the first ILD layer, the gate capping layer, and the SACs to create an air gap spacer.

11. The method of claim 10 , further comprising depositing an air gap seal in an upper portion of the air gap spacer.

12. The method of claim 11 , wherein the air gap seal is made of at least one of ILD, silicon dioxide, silicon dioxide with carbon doping and SiOC.

13. The method of claim 11 , wherein the depositing the air gap seal includes:
depositing a seal layer on a top surface of the substrate; and
performing chemical mechanical polishing (CMP) of the seal layer to define the air gap seal.

14. The method of claim 13 , wherein the seal layer is deposited using plasma-enhanced chemical vapor deposition.

15. The method of claim 13 , further comprising depositing an etch stop layer on the substrate.

16. The method of claim 15 , wherein the etch stop layer includes SiOC.

17. The method of claim 15 , further comprising depositing a second ILD layer on the etch stop layer.

18. The method of claim 17 , further comprising etching portions of the second ILD layer and the etch stop layer to open up selected portions of underlying layers of the substrate.

19. The method of claim 11 , wherein the dummy gate is made of polysilicon.

Assignees

• Lam Res Corp

Inventors

• Besser Paul Raymond
• Van Schravendijk Bart
• Kimura Yoshie
• Delgadino Gerardo A
• Orkorn-Schmidt Harald
• Yang Dengliang

Classifications

• H10W10/20

  Air gaps · CPC title

• H10W10/021 Primary

  of air gaps · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/015

  removing at least parts of gate spacers, e.g. disposable spacers · CPC title