Multigate metal-oxide semiconductor field effect transistor

Patent metadata

Field	Value
Publication number	US-10361202-B2
Application number	US-201715611893-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	Jun 21, 2016
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first region and a second region;
fin type active areas extending in a first direction away from the substrate, the fin type active areas being included in each of the first and second regions;
a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, each of the nanosheets having a channel region;
a gate extending over the fin type active areas in a second direction crossing the first direction, wherein the gate surrounds at least a portion of each of the nanosheets;
a gate dielectric layer interposed between the nanosheets and the gate;
first source and drain regions included in the first region, and second source and drain regions included in the second region, the first source and drain regions and the second source and drain regions being connected to the nanosheets and respectively including materials different from one another; and
insulating spacers interposed between the fin type active areas and the nanosheets, wherein:
air spacers are interposed between the insulating spacers and the first source and drain regions in the first region,
the gate includes a main gate portion on the nanosheets, the main gate portion having a first thickness, and a plurality of sub-gate portions between the nanosheets and the fin type active areas, the sub-gate portions having a second thickness less than the first thickness, and
the insulating spacers cover sidewalls of each of the sub-gate portions, and the gate dielectric layer is interposed between the insulating spacers and the sub-gate portions.

2. The semiconductor device as claimed in claim 1 , wherein, in the second region, the second source and drain regions directly contact and completely cover side surfaces of sidewalls of the insulating spacers opposite the sub-gate portions.

3. The semiconductor device as claimed in claim 1 , wherein a thickness of a lowest sub-gate portion among the plurality of sub-gate portions is greater than respective thicknesses of remaining sub-gate portions.

4. The semiconductor device as claimed in claim 1 , wherein a volume of an air spacer between the insulating spacer covering sidewalls of a lowest sub-gate portion among the plurality of sub-gate portions and the first source and drain regions is different from volumes of the air spacers between the insulating spacers covering sidewalls of the remaining sub-gate portions and the first source and drain regions.

5. The semiconductor device as claimed in claim 4 , wherein a vertical height of the insulating spacer covering the sidewalls of the lowest sub-gate portion among the plurality of sub-gate portions is different from vertical heights of the insulating spacers covering the sidewalls of the remaining sub-gate portions.

6. The semiconductor device as claimed in claim 1 , wherein the first source and drain regions include a semiconductor material including germanium (Ge), and the second source and drain regions include a semiconductor material not including Ge.

7. The semiconductor device as claimed in claim 1 , wherein, in the first source and drain regions, heights of the air spacers decrease in a direction perpendicular to a major surface of the substrate.

8. The semiconductor device as claimed in claim 1 , wherein the air spacers extend from the nanosheets to the fin type active areas.

9. The semiconductor device as claimed in claim 1 , wherein the air spacers project toward the insulating spacers.

10. A semiconductor device, comprising:
a substrate including active areas in each of first and second regions;
at least one nanosheet stack structure facing upper surfaces of the active areas and being spaced apart from the upper surfaces of the active areas, the at least one nanosheet stack structure including a plurality of nanosheets each having a channel region;
a gate extending over the active areas in a direction crossing the active areas, the gate covering the at least one nanosheet stack structure, wherein the gate includes a main gate portion disposed over the at least one nanosheet stack structure and a plurality of sub-gate portions disposed under each of the plurality of nanosheets;
a gate dielectric layer interposed between the at least one nanosheet stack structure and the gate;
first source and drain regions included in the first region, and second source and drain regions included in the second region, the first source and drain regions and the second source and drain regions being connected to the nanosheets;
a first insulating spacer disposed on the plurality of nanosheets, the first insulating spacer covering sidewalls of the gate; and
a plurality of second insulating spacers interposed between the sub-gate portions and the first source and drain regions in spaces between the upper surfaces of the active areas and the at least one nanosheet stack structure and spaces between the plurality of nanosheets in the first region and interposed between the sub-gate portions and the second source and drain regions in spaces between the upper surfaces of the active areas and the at least one nanosheet stack structure and the spaces between the plurality of nanosheets in the second region, wherein air spacers are interposed between the second insulating spacers and the first source and drain regions in the first region, and the second insulating spacers contact the second source and drain regions in the second region.

11. The semiconductor device as claimed in claim 10 , wherein:
the air spacers are respectively disposed between the second insulating spacers and the first source and drain regions, and
volumes of the air spacers differ based on distances between the air spacers and a major surface of the substrate.

12. The semiconductor device as claimed in claim 10 , wherein respective lengths of the sub-gate portions are substantially equal to length of the main gate portion.

13. The semiconductor device as claimed in claim 10 , wherein the first source and drain regions include germanium (Ge) or silicon-germanium (SiGe), and the second source and drain regions include silicon (Si) or silicon carbide (SiC).

14. The semiconductor device as claimed in claim 10 , wherein the second source and drain regions directly contact and cover side surfaces of sidewalls of the second insulating spacers opposite the sub-gate portions, and no air spacers are between the second insulating spacers and the second source and drain regions.

15. A semiconductor device, comprising:
a substrate including a first region and a second region adjacent to each other;
a first nanosheet stack structure in the first region, and a second nanosheet stack structure in the second region, the first and second nanosheet structures each including a lowermost nanosheet coplanar with one another, a metal or metal nitride conductive layer on the lowermost nanosheet, and a second nanosheet on the conductive layer, the second nanosheet having a width greater than that of the conductive layer such that the second nanosheet overhangs the conductive layer to form a recess;
first source and drain regions disposed on opposite sides of the first nanosheet stack structure;
second source and drain regions disposed on opposite sides of the second nanosheet stack structure;
insulating spacers disposed in the recesses of the first and second nanosheet stack structures, the insulating spacers in the recesses of the second nanosheet stack structure contacting the second source and drain regions, and the insulating spacers

Assignees

• Samsung Electronics Co Ltd

Inventors

• Suh Dong-Chan
• Park Gi-Gwan
• Kim Dong-Woo
• Shin Dong-Suk

Classifications

• H01L21/823878

  Electricity · mapped topic

• H01L29/0665

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic