Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10510860-B2
Application number	US-201715801171-A
Country	US
Kind code	B2
Filing date	Nov 1, 2017
Priority date	Aug 29, 2017
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
forming a gate structure over a channel layer and an isolation insulating layer;
forming a first sidewall spacer layer on a side surface of the gate structure;
forming a sacrificial layer so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer;
forming a space between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer;
after the first sidewall spacer layer is removed, forming an air gap between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure;
removing the sacrificial layer; and
forming an interlayer dielectric layer.

2. The method of claim 1 , wherein no air gap is formed on a side surface of the upper portion of the gate structure.

3. The method of claim 1 , further comprising forming a liner layer over the first sidewall spacer layer, before the sacrificial layer is formed.

4. The method of claim 1 , wherein the sacrificial layer includes amorphous silicon.

5. The method of claim 1 , further comprising, before the second sidewall spacer layer is formed, forming a sidewall liner layer at least in the space so as not to completely fill the space.

6. The method of claim 1 , wherein the first sidewall spacer layer includes SiOCN.

7. A method for manufacturing a semiconductor device, the method comprising:
forming a gate structure over a channel layer of a fin structure and an isolation insulating layer;
forming a first sidewall spacer layer on a side surface of the gate structure, the first sidewall spacer layer including a main layer;
forming a liner layer over the first sidewall spacer layer,
forming a sacrificial layer so that an upper portion of the gate structure with the first sidewall spacer layer and the liner layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer and the liner layer is embedded in the first sacrificial layer;
forming a space between the bottom portion of the gate structure and the liner layer by removing the main layer of the first sidewall spacer layer; and
after the first sidewall spacer layer is removed, forming an air gap between the bottom portion of the gate structure and the liner layer by forming a second sidewall spacer layer.

8. The method of claim 7 , wherein the sacrificial layer is formed so that the fin structure is also embedded in the sacrificial layer.

9. The method of claim 7 , wherein:
the first sidewall spacer layer further includes one or more sub-layers, each of which is made of different material than the main layer,
one of the one or more sub-layers is formed on the side surface of the gate structure, and
the space is formed between the one of the one or more sub-layers disposed on the bottom portion of the gate structure and the liner layer.

10. The method of claim 9 , wherein the main layer is thicker than each of the one or more sub-layers.

11. The method of claim 9 , wherein the main layer is made of one selected from the group consisting of silicon oxide, silicon nitride, SiOCN and an insulating metal oxide.

12. The method of claim 9 , wherein the one or more sub-layers are made of SiOCN.

13. The method of claim 7 , wherein:
the first sidewall spacer layer further includes a first sub-layer disposed on the gate structure and a second sub-layer, each which is made of different material than the main layer,
the main layer is disposed between the first and second sub-layers, and
the space is formed between the first sub-layer disposed on the bottom portion of the gate structure and the liner layer.

14. The method of claim 13 , further comprising, before the second sidewall spacer layer is formed, forming a sidewall liner layer at least in the space so as not to completely fill the space.

15. The method of claim 7 , wherein the first sidewall spacer layer consists of the main layer.

16. The method of claim 7 , wherein when forming the space, an upper portion of the liner layer exposed from the sacrificial layer is also removed.

17. The method of claim 7 , wherein:
the gate structure is a dummy gate structure, and
the method further comprising, after the air gap is formed:
forming an interlayer dielectric layer;
removing the dummy gate structure, thereby forming a gate space; and
forming a metal gate structure in the gate space.

18. The method of claim 17 , wherein before forming the interlayer dielectric layer, the sacrificial layer is removed.

19. A method for manufacturing a semiconductor device, the method comprising:
forming a gate structure over a channel layer of a fin structure and an isolation insulating layer;
forming a source epitaxial layer and a drain epitaxial layer over the fin structure not covered by the gate structure;
forming a first sidewall spacer layer on a side surface of the gate structure;
forming a sacrificial layer so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer and the source and drain epitaxial layers are embedded in the first sacrificial layer;
forming a space between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer, such that a part of an upper surface of the isolation insulating layer is exposed to the space; and
after the first sidewall spacer layer is removed, forming an air gap between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

20. The method of claim 19 , wherein the sacrificial layer is made of a dielectric material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chun-Hsiung
• Chang Chia-Hao
• Wang Chih-Hao
• Lien Wai-Yi
• Chou Chih-Chao
• Wang Pei-Yu

Classifications

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic