Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Patent metadata

Field	Value
Publication number	US-10249762-B2
Application number	US-201815938367-A
Country	US
Kind code	B2
Filing date	Mar 28, 2018
Priority date	Aug 26, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, the method comprising:
forming a structure comprising at least an alternating stack of semiconductor layers and metal gate material layers formed on a substrate, a metal gate formed on and in contact with a top layer of the alternating stack, a source region and a drain region in contact with the alternating stack, and dielectric layers formed on and in contact with a top surface of the source and drain regions, respectively;
removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms trenches exposing at least sidewalls of the source and drain regions;
forming a first plurality of interconnects between and in contact with the semiconductor layers and the source region; and
forming a second plurality of interconnects between and in contact with the semiconductor layers and the drain region.

2. The method of claim 1 , further comprising:
prior to removing the portion of the semiconductor layers and metal gate material layers, etching spacers surrounding the source region, the drain region, and the dielectric layers, wherein the etching forms trenches between the metal gate and the dielectric layers and above the portion of the semiconductor layers and metal gate material layers.

3. The method of claim 2 , further comprising:
after the first and second plurality of interconnects have been formed, depositing a spacer material within the trenches.

4. The method of claim 1 , wherein forming the first and second plurality of interconnects forms air pockets between the metal gate material layers and the source region, and between the metal gate material layers and the drain region.

5. The method of claim 1 , wherein forming the structure comprises:
forming an alternating vertical stack of the semiconductor layers and sacrificial semiconductor layers;
forming at least one disposable gate on the alternating vertical stack; and
forming a spacer around the disposable gate and a portion of the alternating vertical stack underlying the disposable gate.

6. The method of claim 5 , further comprising:
forming a cap layer on and in contact with a top portion of the alternating stack of semiconductor layers.

7. The method of claim 5 , wherein forming the structure comprises:
epitaxially growing each semiconductor layer and each sacrificial semiconductor layer in the alternating stack of semiconductor layers and sacrificial semiconductor layers.

8. The method of claim 7 , wherein the forming further comprises:
patterning the alternating stack of semiconductor layers and sacrificial semiconductor layers.

9. The method of claim 5 , wherein forming the structure further comprises:
removing the disposable gate, the removing forming a trench exposing the portion of the alternating vertical stack; and
removing the sacrificial semiconductor layers.

10. The method of claim 9 , wherein forming the structure further comprises
depositing metal gate material within the trench, wherein the depositing forms the metal gate and the metal gate material layers.

11. The method of claim 5 , wherein forming the structure further comprises:
removing a first portion of the alternating vertical stack in a first area corresponding to the source region;
removing a second portion of the alternating vertical stack in a second area corresponding to the drain region; and
epitaxially growing the source region and the drain region within the first and second areas, respectively, wherein the source and drain regions are grown in contact with the portion of the alternating vertical stack underlying the disposable gate.

12. The method of claim 11 , further comprising:
depositing an inter-layer dielectric material on and in contact with the source region and the drain region.

13. The method of claim 1 , further comprising:
forming a cap layer on and in contact with the metal gate.

14. A method for forming a semiconductor structure, the method comprising:
forming an alternating stack of semiconductor layers and metal gate material layers on a substrate;
forming a metal gate on and in contact with a top layer of the alternating stack;
removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms at least one trench; and
forming a plurality of interconnects within the at least one trench, wherein each interconnect in plurality of interconnects contacts a semiconductor layer of the alternating stack, the formation of the plurality of interconnects forms air pockets between pairs of interconnects in the plurality of interconnects.

15. The method of claim 14 , further comprising:
after the plurality of interconnects have been formed, depositing a spacer material within the first and second trenches.

16. The method of claim 14 , wherein forming alternating stack of semiconductor layers and metal gate material layers comprises:
forming an alternating vertical stack of the semiconductor layers and sacrificial semiconductor layers.

17. The method of claim 16 , further comprising:
patterning the alternating vertical stack of semiconductor layers and sacrificial semiconductor layers.

18. The method of claim 16 , further comprising:
removing the sacrificial semiconductor layers, the removing forming voids between the semiconductor layers; and
depositing metal gate material within the voids, wherein the depositing forms the metal gate material layers.

19. The method of claim 14 , wherein forming the metal gate comprises:
forming an alternating vertical stack of the semiconductor layers and sacrificial semiconductor layers;
forming at least one disposable gate on the alternating vertical stack;
forming a spacer around the disposable gate and a portion of the alternating vertical stack underlying the disposable gate;
after forming the spacer, removing the disposable gate, the removing forming a trench exposing the portion of the alternating vertical stack;
removing the sacrificial semiconductor layers; and
depositing metal gate material within the trench, wherein the depositing forms the metal gate and the metal gate material layers.

20. A method for forming a semiconductor structure, the method comprising:
forming a structure comprising at least
a plurality of alternating stacks each comprising semiconductor layers and metal gate material layers formed on a substrate, and a plurality of doped regions each in contact with at least one alternating stack of the plurality of stacks;

removing a portion of each alternating stack of the plurality of stacks in contact with at least one doped region of the plurality of doped regions, the removing forming a plurality of trenches exposing a sidewall of the at least one doped region; and
epitaxially growing a plurality of interconnects within the trenches, wherein each interconnect of the plurality of interconnects is between and in contact with one of the semiconductor layers and one doped region of the plurality of doped regions.

Assignees

• IBM

Inventors

• Bergendahl Marc A
• Cheng Kangguo
• Miller Eric R
• Sporre John R
• Teehan Sean

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/78618 Primary

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic