Air gap spacer with wrap-around etch stop layer under gate spacer

Patent metadata

Field	Value
Publication number	US-10411114-B2
Application number	US-201715851149-A
Country	US
Kind code	B2
Filing date	Dec 21, 2017
Priority date	Dec 21, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

Semiconductor devices and methods are provided to fabricate FET devices. For example, a semiconductor device can include a functional gate structure on a channel region of a fin structure; and a source/drain region on each side of the functional gate structure. The functional gate structure has an insulator material abutting a portion of the sidewalls of the functional gate structure and the source drain region and the top surface of the fin, with a top surface of the insulator material in contact with a bottom surface of the first spacer layer. The functional gate structure further includes a dielectric top layer. The dielectric top layer seals an air gap between the top surface of the insulator material and the dielectric top layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a semiconductor structure comprising a functional gate structure on a channel region of a fin structure, wherein the functional gate structure comprises a metal gate, a first spacer layer and an insulator material abutting sidewalls of the functional gate structure and metal gate with a top surface of the insulator material in contact with a bottom surface of the first spacer layer, and a capping layer on a top surface of the metal gate and abutting sidewalls of the spacer layer; and a source/drain region on each side of the functional gate structure;
removing the capping layer and the first spacer layer and exposing the top surface of the insulator material to provide a spacer opening adjacent the sidewalls of the metal gate and above a top surface of the metal gate; and
depositing a dielectric top layer in a portion of the spacer opening and on the top surface of the metal gate, wherein the dielectric top layer seals an air gap positioned in the dielectric top layer, wherein a bottom surface of the air gap is above the top surface of the insulator material.

2. The method of claim 1 , wherein a top surface of the semiconductor structure includes a shallow trench isolation layer.

3. The method of claim 1 , wherein forming the fin structure comprises depositing a hardmask layer on a semiconductor substrate, and etching the hardmask layer and semiconductor substrate to form the fin structure.

4. The method of claim 1 , wherein the insulator material is a low-k insulator material.

5. The method of claim 4 , wherein the low-k insulator material is silicon oxycarbide.

6. The method of claim 1 , wherein the source/drain region is an epitaxially grown source/drain on the fin structure.

7. The method of claim 1 , wherein the step of forming the semiconductor structure comprises:
forming a sacrificial gate structure on a channel region of a fin structure, wherein the sacrificial gate structure has a first spacer layer and an insulator material abutting sidewalls of the functional gate structure with a top surface of the insulator material in contact with a bottom surface of the first spacer layer;
forming the source/drain region on each side of the sacrificial gate structure and in contact with the first spacer layer, wherein the source/drain region on each side of the sacrificial gate structure is in contact with the fin structure; and
replacing the sacrificial gate structure with the functional gate structure.

8. The method of claim 1 , wherein the step of forming the semiconductor structure comprises:
forming a sacrificial gate structure on the channel region of the fin structure of the semiconductor structure, the sacrificial gate structure having a first and second spacer layer abutting the sidewalls of the sacrificial gate structure;
laterally etching the exterior surface of the first and second spacer layers to expose the exterior surface of the sacrificial gate structure and the fin structure,
depositing the insulator material on the exterior surfaces of the sacrificial gate structure and the first and second spacer layer including the exposed portion of the exterior surface of the sacrificial gate structure and the fin structure;
selectively etching the insulator material and the second sacrificial spacer layer to form a void under a bottom portion of the second spacer layer that exposes the insulator material on the sacrificial gate structure;
removing the second sacrificial spacer layer;
forming the source/drain region and trench contact on each side of a sacrificial gate structure and in contact with the first spacer layer, wherein the source/drain region on each side of the sacrificial gate structure is in contact with the fin structure; and
replacing the sacrificial gate structure with the functional gate structure having the capping layer thereon.

9. The method of claim 1 , wherein the air gap is continuous from the top surface of the insulator material to a pinch-off region defined by an underlying surface of the dielectric top layer that seals the air gap.

10. The method of claim 1 , wherein the air gap is sealed between the dielectric top layer and the top surface of the insulator material.

11. The method of claim 1 , wherein the fin structure comprises a semiconductor portion, and the semiconductor portion of the fin structure comprises a group IV semiconductor material, a group II semiconductor material, a group VI semiconductor material, a group III semiconductor material, and a group V semiconductor material, or combinations thereof.

12. The method of claim 8 , wherein the insulator material is a low-k insulator material.

13. The method of claim 1 , wherein the capping layer and the first spacer layer are removed by a reactive ion etching process.

14. The method of claim 1 , wherein the dielectric top layer is SiN or SiBCN.

15. The method of claim 1 , wherein the gate structure comprises a layer of a high-k material.

16. The method of claim 7 , wherein the insulator material is a low-k insulator material.

17. The method of claim 16 , wherein the low-k insulator material is silicon oxycarbide.

18. The method of claim 7 , wherein the source/drain region is an epitaxially grown source/drain on the fin structure.

19. The method of claim 12 , wherein the low-k insulator material is silicon oxycarbide.

20. The method of claim 8 , wherein the source/drain region is an epitaxially grown source/drain on the fin structure.

Assignees

• IBM

Inventors

• Zhang Chen
• Cheng Kangguo
• Miao Xin
• Xu Wenyu
• Xu Peng

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H01L29/66553

  Electricity · mapped topic