Devices including gate spacer with gap or void and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9559184-B2
Application number	US-201514739977-A
Country	US
Kind code	B2
Filing date	Jun 15, 2015
Priority date	Jun 15, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

First claim

What is claimed is:

1. A structure comprising:
a substrate with a fin;
a gate stack over the fin;
a contact over the substrate; and
a spacer disposed laterally between the gate stack and the contact, the spacer comprising a first dielectric sidewall portion and a second dielectric sidewall portion, a void being disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

2. The structure of claim 1 , wherein the first dielectric sidewall portion and the second dielectric sidewall portion each comprises a low-k dielectric material.

3. The structure of claim 1 , wherein the spacer comprises a solid dielectric material fully enclosing the void within the solid dielectric material, the first dielectric sidewall portion and the second dielectric sidewall portion each being a portion of the solid dielectric material.

4. The structure of claim 1 , wherein the spacer comprises a first solid dielectric layer and a second solid dielectric layer, each of the first solid dielectric layer and the second solid dielectric layer extending vertically from the substrate, the first solid dielectric layer being the first dielectric sidewall portion, the second solid dielectric layer being the second dielectric sidewall portion, a solid dielectric material being disposed between the first solid dielectric layer and the second solid dielectric layer above the void.

5. The structure of claim 1 , wherein the void contacts a surface of the substrate.

6. The structure of claim 1 , wherein the spacer laterally encircles the gate stack, and the void laterally encircles the gate stack.

7. The structure of claim 1 , wherein the spacer has a first height from a surface of the substrate and in a direction normal to the surface of the substrate, the void having a second height from a bottom surface of the void to a top surface of the void, a ratio of the second height to the first height being in a range from 0.3 to 0.7.

8. The structure of claim 1 further comprising:
a source/drain region in the substrate and proximate to the gate stack, the contact connecting to the source/drain region;
a first inter-layer dielectric layer over the substrate and laterally around the gate stack, the contact being disposed through the first inter-layer dielectric layer; and
a second inter-layer dielectric layer over the first inter-layer dielectric layer, the contact, the gate stack, and the spacer.

9. The structure of claim 8 further comprising:
a first dielectric cap over the contact and the first inter-layer dielectric layer; and
a second dielectric cap over the gate stack, respective top surfaces of the first dielectric cap, the second dielectric cap, and the spacer being co-planar.

10. A structure comprising:
a substrate;
a gate dielectric over the substrate;
a gate electrode over the gate dielectric;
a gate spacer around the gate electrode, the gate spacer comprising a first solid dielectric sidewall portion and a second solid dielectric sidewall portion, a void being between the first solid dielectric sidewall portion and the second solid dielectric sidewall portion, the void being around the gate electrode;
a source/drain region in the substrate and proximate to the gate dielectric and gate electrode; and
a lower contact connecting to the source/drain region, the gate spacer being disposed immediately adjacent to the lower contact and between the lower contact and the gate electrode.

11. The structure of claim 10 , wherein the spacer comprises a continuous layer enclosing the void, each of the first solid dielectric sidewall portion and the second solid dielectric sidewall portion being a portion of the continuous layer.

12. The structure of claim 10 , wherein the first solid dielectric sidewall portion is a first layer, and the second solid dielectric sidewall portion is a second layer separated from the first layer, the void being disposed between the first layer and the second layer, the void contacting a surface of the substrate, a solid dielectric material being disposed between the first layer and the second layer and above the void.

13. The structure of claim 10 further comprising:
a first inter-layer dielectric layer over the substrate, the gate electrode being in the first inter-layer dielectric layer, the lower contact being through the first inter-layer dielectric layer;
a first dielectric cap over the gate electrode;
a second dielectric cap over the lower contact, top surfaces of the first dielectric cap, the second dielectric cap, and the gate spacer being co-planar;
a second inter-layer dielectric layer over the first dielectric cap, the second dielectric cap, and the gate spacer;
a first upper contact extending through the second inter-layer dielectric layer and the first dielectric cap and connecting to the gate electrode; and
a second upper contact extending through the second inter-layer dielectric layer and the second dielectric cap and connecting to the lower contact.

14. A structure comprising:
a gate dielectric over a substrate;
a gate electrode over the gate dielectric;
a contact in physical connection with the substrate at a point laterally removed from the gate electrode;
a dielectric material surrounding the gate electrode and at least partially located between the gate electrode and the contact, the dielectric material comprising a first material throughout the dielectric material, wherein the dielectric material comprises a first sidewall facing the contact, the first sidewall being straight as the first sidewall extends from a first side of the dielectric material facing the substrate to a second side of the dielectric material opposite the first side; and
a void surrounded by the dielectric material, wherein the void encircles the gate electrode.

15. The structure of claim 14 , wherein the dielectric material has a first height and the void has a second height that is between about 0.3 and 0.7 times the first height.

16. The structure of claim 14 , wherein the void exposes a portion of the substrate.

17. The structure of claim 14 , further comprising an inter-layer dielectric surrounding the contact.

18. The structure of claim 14 , further comprising a dielectric cap located over the gate electrode.

19. The structure of claim 18 , wherein the dielectric cap has a top surface that is planar with a top surface of the dielectric material.

20. The structure of claim 14 , wherein a portion of the dielectric material is interposed between the void and the substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Tsai Ching-Wei
• Liu Chi-Wen
• Leung Ying-Keung

Classifications

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title