Full air-gap spacers for gate-all-around nanosheet field effect transistors

Patent metadata

Field	Value
Publication number	US-10553696-B2
Application number	US-201715819708-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Nov 21, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Semiconductor devices and method of forming the same include forming a stack of vertically aligned, alternating layers including sacrificial layers and channel layers. The sacrificial layers are recessed relative to the channel layers to form recesses. A dual-layer dielectric is deposited. The dual-layer dielectric includes a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the recesses. The first dielectric material is recessed relative to the second dielectric material. The second dielectric material is etched away to create air gaps. Outer spacers are formed using a third dielectric material that pinches off, preventing the third dielectric material from filling the air gaps.

First claim

The invention claimed is:

1. A method of forming a semiconductor device, comprising:
forming a stack of vertically aligned, alternating layers comprising sacrificial layers and channel layers;
recessing the sacrificial layers relative to the channel layers to form recesses;
depositing a dual-layer dielectric, comprising a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the recesses;
recessing the first dielectric material relative to the second dielectric material to form recesses;
depositing additional second dielectric material to fill the recesses;
etching away the second dielectric material and the additional second dielectric material to create air gaps; and
forming outer spacers using a third dielectric material that pinches off, preventing the third dielectric material from filling the air gaps.

2. The method of claim 1 , wherein the first dielectric material is silicon nitride, the second dielectric material is silicon dioxide, and the third dielectric material is silicoboron carbonitride.

3. The method of claim 1 , further comprising:
etching away the sacrificial layers; and
forming a gate stack on and around the channel layers.

4. The method of claim 1 , wherein forming the outer spacers comprises pinching off the outer spacers to form air gaps within the outer spacers.

5. The method of claim 1 , wherein the first dielectric material is formed to a thickness between about 1 nm and about 2 nm.

6. The method of claim 1 , further comprising growing source and drain regions from exposed sidewalls of the channel layers.

7. The method of claim 6 , wherein the source and drain regions are formed after the additional second dielectric material is deposited and before the second dielectric material and the additional second dielectric material are etched away.

8. The method of claim 6 , further comprising forming source and drain contacts to provide electrical connectivity to the source and drain regions.

9. The method of claim 8 , wherein forming the outer spacers is performed after forming the source and drain contacts.

10. The method of claim 8 , further comprising depositing an encapsulating layer over the source and drain regions, before forming the source and drain contacts.

11. The method of claim 10 , wherein the encapsulating layer is formed from additional second dielectric material and wherein etching away the second dielectric material further comprises etching away the encapsulating layer.

12. A method of forming a semiconductor device, comprising:
forming a stack of vertically aligned, alternating layers comprising sacrificial layers and channel layers;
growing source and drain regions from exposed sidewalls of the channel layers;
forming source and drain contacts to provide electrical connectivity to the source and drain regions;
forming outer spacers using a first dielectric material that pinches off to form air gaps within the outer spacers after forming the source and drain contacts; and
forming inner spacers between the channel layers that each include a recessed layer of second dielectric material and an air gap, wherein forming the outer spacers also pinches off to form the air gap in each inner spacer.

13. The method of claim 12 , wherein forming the inner spacers comprises:
recessing the sacrificial layers relative to the channel layers to form recesses;
depositing a dual-layer dielectric, comprising the second dielectric material formed conformally on surfaces of the recesses and a third dielectric material filling a remainder of the recesses;
recessing the second dielectric material relative to the third dielectric material to form recesses;
depositing additional third dielectric material to fill the recesses; and
etching away the third dielectric material to create the air gaps included in the inner spacers.

14. The method of claim 13 , further comprising depositing an encapsulating layer over the source and drain regions, before forming the source and drain contacts.

15. The method of claim 14 , wherein the encapsulating layer is formed from additional third dielectric material and wherein etching away the third dielectric material further comprises etching away the encapsulating layer.

16. The method of claim 12 , wherein the first dielectric material is silicoboron carbonitride and the second dielectric material is silicon nitride.

17. The method of claim 12 , further comprising:
etching away the sacrificial layers; and
forming a gate stack on and around the channel layers.

Assignees

• IBM

Inventors

• Ando Takashi
• Hashemi Pouya
• Lee Choonghyun
• Reznicek Alexander
• Zhang Jingyun

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title