Method to form air-gap spacers and air-gap spacer-containing structures

Patent metadata

Field	Value
Publication number	US-10164104-B2
Application number	US-201615343590-A
Country	US
Kind code	B2
Filing date	Nov 4, 2016
Priority date	Nov 4, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A device includes an air-gap (i.e., air-gap spacer) formed in situ during the selective, non-conformal deposition of a conductive material. The air-gap is disposed between source/drain contacts and a gate conductor of the device and beneath a portion of the conductive material, and is configured to decrease capacitive coupling between adjacent conductive elements. Prior to deposition of the conductive material, source/drain contact structures are recessed and a selective etch is used to remove sidewall spacers that are disposed between the source/drain contacts and the gate structures.

First claim

What is claimed is:

1. A method of forming a fin field effect transistor (FinFET) device, comprising:
forming a source/drain junction over each of a source region and a drain region of a semiconductor fin;
forming a conductive contact over each of the source/drain junctions;
forming a gate stack over a channel region of the fin between the source/drain junctions, wherein the gate stack is separated from the source/drain junctions by spacers;
recessing the conductive contacts to expose the spacers;
removing the spacers from between the source/drain junctions and the gate stack; and
selectively depositing a conductive layer over each of the conductive contacts to form air-gaps between the gate stack and the recessed conductive contacts and beneath a portion of the conductive layer.

2. The method of claim 1 , wherein the source/drain junctions are formed by selective epitaxy directly on the source and drain regions of the fin.

3. The method of claim 1 , wherein the gate stack is formed over sidewalls of the spacers.

4. The method of claim 1 , further comprising forming a gate cap over the gate stack.

5. The method of claim 4 , wherein conductive layer impinges a sidewall of the gate cap.

6. The method of claim 1 , wherein a top surface of the recessed conductive contact is at or above a top surface of the gate stack.

7. The method of claim 1 , wherein the conductive layer is deposited by electroless deposition.

8. The method of claim 1 , wherein the conductive layer forms a top surface of the air-gaps.

9. A method of forming a fin field effect transistor (FinFET) device, comprising:
forming a fin over a semiconductor substrate;
forming a source/drain junction over each of a source region and a drain region of the fin;
forming an interlayer dielectric comprising a first dielectric material over the source/drain junctions;
forming spacers comprising a second dielectric material over sidewalls of the source/drain junctions and over sidewalls of the interlayer dielectric;
forming a gate stack over a channel region of the fin and over sidewalls of the spacers between adjacent source/drain junctions;
recessing the gate stack to form an opening over the gate stack and depositing a gate cap within the opening;
etching the interlayer dielectric to expose the source/drain junctions;
forming conductive contacts in electrical contact with the exposed portions of the source/drain junctions;
recessing the conductive contacts to expose the spacers;
removing the spacers; and
selectively depositing a conductive layer over the recessed conductive contacts to form an air-gap between the recessed conductive contact and the gate stack and beneath a portion of the conductive layer.

10. The method of claim 9 , wherein sidewalls of the interlayer dielectric are aligned with sidewalls of the source/drain junctions.

11. The method of claim 9 , wherein the spacers are removed selective to the gate cap.

Assignees

• Globalfoundries Inc

Inventors

• Zhang Xunyuan
• Xie Ruilong

Classifications

• H01L29/66795

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L29/518

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic