Stacked nanosheet field-effect transistor with air gap spacers

Patent metadata

Field	Value
Publication number	US-10269983-B2
Application number	US-201715590409-A
Country	US
Kind code	B2
Filing date	May 9, 2017
Priority date	May 9, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.

First claim

What is claimed is:

1. A structure for a field-effect transistor, the structure comprising:
a fin including a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack;
a gate structure including a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer;
a source/drain region connected with a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer; and
an air gap spacer including a cavity surrounded by the portion of the first nanosheet channel layer, the portion of the second nanosheet channel layer, the section of the gate structure, and the source/drain region, and the source/drain region is arranged to close and seal the cavity.

2. The structure of claim 1 further comprising:
a conformal dielectric layer including a first portion arranged between the air gap spacer and the section of the gate structure.

3. The structure of claim 2 wherein the conformal dielectric layer includes a second portion arranged between the portion of the first nanosheet channel layer and the air gap spacer, and the conformal dielectric layer includes a third portion arranged between the portion of the second nanosheet channel layer and the air gap spacer.

4. The structure of claim 2 wherein the conformal dielectric layer is comprised of silicon nitride.

5. The structure of claim 2 wherein the fin is located on a substrate, the substrate includes a dielectric layer adjacent to the fin, the conformal dielectric layer has a portion located on the dielectric layer, and the fin and the portion of the conformal dielectric layer mask a first area on the dielectric layer.

6. The structure of claim 5 wherein the dielectric layer includes a second area adjacent to the first area, and the dielectric layer is thinner in the second area than in the first area.

7. The structure of claim 6 wherein the source/drain region is arranged over the dielectric layer in the second area.

8. The structure of claim 1 wherein the air gap spacer is arranged horizontally between the section of the gate structure and the source/drain region.

9. The structure of claim 8 wherein the air gap spacer is arranged vertically between the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer.

10. A method for forming a field-effect transistor, the method comprising:
forming a first fin that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack;
forming a cavity between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer;
epitaxially growing a source/drain region connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer; and
forming a first gate structure including a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer,
wherein the cavity is surrounded by the portion of the first nanosheet channel layer, the portion of the second nanosheet channel layer, the section of the first gate structure, and the source/drain region to define an air gap spacer, and the source/drain region is arranged to close and seal the cavity.

11. The method of claim 10 wherein the first nanosheet channel layer includes a first vertical surface, the second nanosheet channel layer includes a second vertical surface, the first nanosheet channel layer is separated from the second nanosheet channel layer by a sacrificial semiconductor layer, and forming the cavity between the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer comprises:
laterally recessing the sacrificial semiconductor layer relative to the first vertical surface and the second vertical surface to form the cavity.

12. The method of claim 11 further comprising:
depositing a conformal dielectric layer inside the cavity; and
depositing a dielectric layer that fills the cavity to form a dielectric spacer and that covers the first vertical surface and the second vertical surface.

13. The method of claim 12 further comprising:
removing the dielectric layer from the first vertical surface and the second vertical surface with an isotropic etching process.

14. The method of claim 13 wherein the conformal dielectric layer is deposited on the first vertical surface and the second vertical surface, the dielectric layer is removed by the isotropic etching process from the first vertical surface and the second vertical surface without removing the dielectric spacer from the cavity, and further comprising:
before the source/drain region is epitaxially grown, removing the dielectric spacer from the cavity, the conformal dielectric layer from the first vertical surface, and the conformal dielectric layer from the second vertical surface.

15. The method of claim 14 wherein the removal of the conformal dielectric layer from the first vertical surface and the second vertical surface exposes the first vertical surface and the second vertical surface for epitaxial growth of the source/drain region.

16. The method of claim 12 wherein the first fin and the first gate structure are separated by a gap from a second fin and a second gate structure, the dielectric layer fills the gap, and further comprising:
removing the dielectric layer from the gap with an anisotropic etching process.

17. The method of claim 16 wherein the conformal dielectric layer is deposited on the first vertical surface and the second vertical surface, the dielectric layer is removed by the anisotropic etching process from the gap without removing the dielectric spacer from the cavity, and further comprising:
before the source/drain region is epitaxially grown, removing the dielectric spacer from the cavity, the conformal dielectric layer from the first vertical surface, and the conformal dielectric layer from the second vertical surface.

18. The method of claim 16 wherein the removal of the conformal dielectric layer from the first vertical surface and the second vertical surface exposes the first vertical surface and the second vertical surface for epitaxial growth of the source/drain region.

19. The method of claim 16 wherein the dielectric spacer is comprised of an organic planarization layer (OPL) material or silicon dioxide, and the conformal dielectric layer is comprised of silicon nitride.

20. A structure for a field-effect transistor, the structure comprising:
a fin including a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack;
a gate structure including a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer;
a source/drain region connected with a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer;
an air gap spacer surrounded by the portion of the first nanosheet channel layer, the portion of the second nanosheet channel layer, the section of the gate structure, and the source/drain region; and
a conformal dielectric layer includes a first portion arranged between the air gap spacer and the section of the gate structure,
wherein the fin is located on a substrate, the substrate includes a dielectric layer adjacent to the fin, the conformal dielectric layer has a portion located on the dielectric layer, the fin and the portion of the conformal dielectric layer mask a fi

Assignees

• Globalfoundries Inc

Inventors

• Frougier Julien
• Xie Ruilong
• Zang Hui
• Cheng Kangguo
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H01L29/66795

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/0665

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic