Methods for forming self-aligned contacts using spin-on silicon carbide

Patent metadata

Field	Value
Publication number	US-12080599-B2
Application number	US-202217959557-A
Country	US
Kind code	B2
Filing date	Oct 4, 2022
Priority date	Feb 17, 2021
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

First claim

What is claimed is:

1. A method to protect a feature on a substrate, the method comprising:
providing a plurality of first features and a plurality of second features on the substrate;
forming a first cap layer over the plurality of first features;
forming a second cap layer over the plurality of second features, wherein the second cap layer is formed by spin coating a material onto the substrate and comprises a different material from the first cap layer;
forming a dielectric layer on the substrate;
utilizing a first etch process to etch portions of the dielectric layer and the first cap layer according to a first masking pattern formed above the dielectric layer to form a plurality of first self-aligned contacts to the plurality of first features; and
utilizing a second etch process to selectively etch portions of the dielectric layer and the second cap layer according to a second masking pattern formed above the dielectric layer to form a plurality of second self-aligned contacts to the plurality of second features, the first etch process selectively etching the first cap layer relative to the second cap layer, and the second etch process selectively etching the second cap layer relative to the first cap layer.

2. The method of claim 1 , wherein the material is a dielectric material.

3. The method of claim 1 , wherein the material comprises SiC.

4. The method of claim 1 , wherein the material is provided as methyl silsesquioxane (MSQ).

5. The method of claim 1 , wherein the material is provided as polycarbosilane (PCS).

6. The method of claim 1 , wherein after the spin on process is performed a planarization technique is performed to remove the material from portions of the substrate other than the plurality of second features.

7. A method of processing a substrate, the method comprising:
spin-on coating to form a SiC layer covering a first conductive feature over the substrate;
providing a cap layer covering a second conductive feature disposed over the substrate; and
exposing the SiC layer and the cap layer to a first etching process to selectively remove the SiC layer relative to the cap layer and expose the first conductive feature.

8. The method of claim 7 , further comprising:
exposing the remaining SiC layer and the cap layer to a second etching process to selectively remove the cap layer and expose the second conductive feature.

9. The method of claim 8 , wherein exposing the remaining SiC layer and the cap layer to the second etching process comprises plasma etching using fluoromethane based plasma etch chemistry.

10. The method of claim 7 , wherein the cap layer comprises a silicon nitride layer.

11. The method of claim 7 , wherein exposing the SiC layer and the cap layer to the first etching process comprises plasma etching using chlorine-oxygen (Cl 2 /O 2 ) plasma etch chemistry.

12. The method of claim 7 , wherein the spin-on coating comprises using methyl silsesquioxane (MSQ) to form the SiC layer.

13. The method of claim 7 , wherein the spin-on coating comprises using polycarbosilane (PCS) to form the SiC layer.

14. A method for processing a substrate, the method comprising:
forming, over the substrate, a first feature covered with a first dielectric layer comprising a first dielectric material;
forming, over the substrate, a second feature covered with a second dielectric layer comprising a second dielectric material different from the first dielectric material;
exposing the substrate to a first etching process to selectively remove the first dielectric layer and expose the first feature;
exposing the substrate to a second etching process to selectively remove the second dielectric layer and expose the second feature; and
depositing a conductive material to form a first contact to the first feature and a second contact to the second feature.

15. The method of claim 14 , wherein the first etching process etches the first dielectric material at least 20 times faster than the second dielectric material.

16. The method of claim 14 , wherein the second etching process etches the second dielectric material at least 3 times faster than the first dielectric material.

17. The method of claim 14 , wherein the first dielectric material comprises SiC and the second dielectric material comprises SiN.

18. The method of claim 14 , wherein exposing the substrate to a first etching process comprises plasma etching using chlorine-oxygen (Cl 2 /O 2 ) plasma etch chemistry.

19. The method of claim 14 , wherein exposing the substrate to a second etching process comprises plasma etching using fluoromethane based plasma etch chemistry.

20. The method of claim 14 , further comprising spin-on coating to form the first dielectric layer covering the first feature.

Assignees

• Tokyo Electron Ltd

Inventors

• Sun Junling
• Huli Lior
• Metz Andrew
• Raley Angelique

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title