Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-10460993-B2
Application number	US-201715859327-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Nov 30, 2017
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction;
a first isolation structure separating a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction, the first isolation structure having a width along the first direction, the first end of the first portion of the fin having a surface roughness;
a gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin, wherein the gate structure has the width along the first direction, and wherein a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the first direction; and
a second isolation structure over a second end of a first portion of the fin, the second end opposite the first end, the second isolation structure having the width along the first direction, and the second end of the first portion of the fin having a surface roughness less than the surface roughness of the first end of the first portion of the fin, wherein a center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the first direction.

2. The integrated circuit structure of claim 1 , wherein the first end of the first portion of the fin has a scalloped topography.

3. The integrated circuit structure of claim 1 , further comprising:
a first epitaxial semiconductor region on the first portion of the fin between the gate structure and the first isolation structure; and
a second epitaxial semiconductor region on the first portion of the fin between the gate structure and the second isolation structure.

4. The integrated circuit structure of claim 3 , wherein the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, the width along the second direction wider than a width of the first portion of the fin along the second direction beneath the gate structure.

5. The integrated circuit structure of claim 1 , the gate structure further comprising a high-k dielectric layer between the gate electrode and the first portion of the fin and along sidewalls of the gate electrode.

Assignees

• Intel Corp

Inventors

• Ghani Tahir
• Ho Byron
• Ward Curtis W
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title