Self aligned active trench contact

Patent metadata

Field	Value
Publication number	US-9245894-B2
Application number	US-201414563203-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Dec 12, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.

First claim

What is claimed is:

1. A method of forming an integrated circuit, comprising the steps of:
forming a plurality of gate structures over a substrate, by a process comprising the steps of forming a plurality of gates over the substrate, and forming sidewalls of dielectric material abutting lateral surfaces of the gates;
forming source/drain regions in the substrate adjacent to the gate structures;
forming a gapfill dielectric layer over the substrate between the gate structures, so that a top surface of the gapfill dielectric layer is substantially coplanar with top surfaces of the gate structures;
forming a contact mask over the gapfill dielectric layer which exposes areas for self-aligned contacts, at least some of the areas for the self-aligned contacts overlapping adjacent instances of the gate structures;
removing the gapfill dielectric layer in the areas for the self-aligned contacts;
forming a layer of contact metal over the gate structures, extending between the gate structures in the areas for the self-aligned contacts;
removing the contact metal from over the gate structures by a planarization process to form the self-aligned contacts, so that a plurality of the self-aligned contacts make electrical connections to the source/drain regions and abut the gate structures along heights of the gate structures, and so that a top surface of each of the self-aligned contacts is not higher than a top surface of the gate structure abutting the self-aligned contact;
forming a PMD layer over the gate structures and the self-aligned contacts;
forming vias through the PMD layer; and
forming metal interconnects on the vias.

2. The method of claim 1 , further comprising the step of forming metal silicide on the source/drain regions prior to the step of forming the gapfill dielectric layer.

3. The method of claim 1 , further comprising the step of forming metal silicide on the source/drain regions after the step of removing the gapfill dielectric layer in areas for self-aligned contacts.

4. The method of claim 1 , wherein an instance of the self-aligned contacts is formed between, and abuts each of, two instances of the gate structures.

5. The method of claim 1 , wherein:
the contact mask exposes an area for a first instance of the self-aligned contacts on a first side of an instance of the gate structures and an area for a second instance of the self-aligned contacts on a second, opposite, side of the instance of the gate structures, the area for the first instance of the self-aligned contacts being contiguous with the area for the second instance of the self-aligned contacts; and
the step of removing the contact metal from over the gate structures forms the first instance of the self-aligned contacts on the first side of, and abutting, the instance of the gate structures, and forms the second instance of the self-aligned contacts on a second, opposite, side of, and abutting, the instance of the gate structures.

6. The method of claim 1 , wherein:
the contact mask exposes an area for a local interconnect over field oxide, the area for the local interconnect being contiguous with an instance of an area for an instance of the self-aligned contacts; and
the step of removing the contact metal from over the gate structures forms the local interconnect, so that the local interconnect is contiguous with the instance of the self-aligned contacts.

7. The method of claim 6 , wherein:
the contact mask exposes an area for a first instance of the self-aligned contacts over a source/drain region of a PMOS transistor of a logic gate, and an area for a second instance of the self-aligned contacts over a source/drain region of an NMOS transistor of the logic gate, the area for the first instance of the self-aligned contacts and the area for the second instance of the self-aligned contacts being contiguous with the area for the local interconnect; and
the step of removing the contact metal from over the gate structures forms the first instance of the self-aligned contacts, the second instance of the self-aligned contacts and the local interconnect, so that the first instance of the self-aligned contacts and the second instance of the self-aligned contacts are electrically connected through the local interconnect which is contiguous with the first instance of the self-aligned contacts and the second instance of the self-aligned contacts.

8. The method of claim 1 , wherein an instance of the self-aligned contacts is formed between, and abuts both of, two instances of the gate structures in a logic gate.

9. The method of claim 1 , wherein:
the integrated circuit comprises a plurality of contiguous SRAM cells;
the contact mask exposes:
an area for a first instance of the self-aligned contacts between two adjacent PMOS load transistors;
an area for a second instance of the self-aligned contacts adjacent to a first of the two adjacent PMOS load transistors, opposite from the area for the first instance of the self-aligned contacts;
an area for a third instance of the self-aligned contacts adjacent to a second of the two adjacent PMOS load transistors, opposite from the area for the first instance of the self-aligned contacts, the area for the first instance of the self-aligned contacts, the area for the second instance of the self-aligned contacts, and the area for the third instance of the self-aligned contacts being contiguous;
an area for a fourth instance of the self-aligned contacts between two adjacent NMOS driver transistors;
an area for a fifth instance of the self-aligned contacts between two adjacent NMOS passgate transistors; and
an area for a sixth instance of the self-aligned contacts between a first of the two adjacent NMOS driver transistors and first of the two adjacent NMOS passgate transistor, the area for the fourth instance of the self-aligned contacts, the area for the fifth instance of the self-aligned contacts, and the area for the sixth instance of the self-aligned contacts being contiguous.

10. The method of claim 1 , further comprising the step of forming a sidewall extension layer on the sidewalls after the step of forming the source/drain regions and prior to the step of forming the gapfill dielectric layer.

11. The method of claim 1 , further comprising the steps of removing the gates and forming replacement gates, after the step of removing the contact metal from over the gate structures.

12. The method of claim 1 , further comprising the steps of removing the gates and forming replacement gates, after the step of forming a gapfill dielectric layer and prior to the step of forming the contact mask.

Assignees

• Texas Instruments Inc

Inventors

• Lytle Steven Alan

Classifications

• H10P14/414

  of metal-silicide materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title