Method of forming self-aligned contacts using a replacement metal gate process in a semiconductor device

Patent metadata

Field	Value
Publication number	US-9257529-B2
Application number	US-201414203838-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Mar 11, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Techniques disclosed herein provide a gate pitch scaling solution for creating source/drain contacts in a replacement metal gate fabrication scheme. Such techniques provide a self-aligned contact process that protects gate electrodes from shorts due to etching from misaligned patterns. Techniques herein provide a dual layer cap formed by making a semi conformal material deposition over a non-planar topography of RMG formation structures, and using selective etching and planarization to yield a dual layer protective cap that does not excessively increase an aspect ratio.

First claim

The invention claimed is:

1. A method of forming self-aligned contacts in a semiconductor device, the method comprising:
receiving a substrate having a first structure of a first material composition and a Second structure of a second material composition, the second structure being formed immediately adjacent to the first structure, the first structure and second structure being of different heights such that together the first structure and the second structure defining a first topography that is non-planar at an upper surface thereof;
depositing a first layer on the first topography, the first layer being partially conformal resulting in the first layer defining a second topography, the first layer defining a valley over the first structure and forming a peak over the second structure;
depositing a second layer on the first layer, the second layer being sufficiently thick to fill the defined valley and cover the peak of the second topography;
planarizing the second layer down to the first layer above the second structure such that the peak in the first layer is exposed while the defined valley remains filled with the second layer; and
etching exposed portions of the first layer down until reaching the second structure beneath the first layer, the second layer in the defined valley functioning as a hard mask that impedes etching of the first layer above the first structure relative to etching of the first layer above the second structure.

2. The method of claim 1 , further comprising:
depositing a third layer that fills gaps in the first layer and that covers the first layer.

3. The method of claim 2 , further comprising:
executing a self-aligned contact etch process that etches through the third layer and the second structure.

4. The method of claim 3 , further comprising filling an etched self-aligned contact passage with a metalized contact.

5. The method of claim 3 , wherein receiving the substrate having a first structure of a first material composition and a second structure of a second material composition includes preparing a replacement metal gate (RMG) structure of a gate device on a semiconductor substrate, the RMG structure having a metal gate electrode being the first structure of the first material composition, the metal gate electrode having a side barrier layer and a silicon oxide spacer in contact with the side barrier layer, the silicon oxide spacer being the second structure of the second material, wherein the metal gate electrode and the silicon oxide spacer being different heights includes creating a recess in the metal gate electrode from an initially planarized RMG structure.

6. The method of claim 5 , wherein the RMG structure was formed by using double patterning or side wall image transfer.

7. The method of claim 5 , wherein the first layer is a dielectric cap layer, and wherein the second layer and the third layer are silicon oxide layers.

8. The method of claim 7 , wherein gate pitch is 64 nm or less.

9. The method of claim 7 , wherein the metal gate electrode is a tungsten plug.

10. The method of claim 7 , wherein preparing the replacement metal gate (RMG) structure of the gate device on the semiconductor substrate includes preparing the RMG structure of a fin field effect transistor (FinFET).

11. The method of claim 7 , wherein depositing the dielectric cap layer on the RMG structure includes depositing a conformal layer of silicon nitride.

12. The method of claim 11 , wherein etching exposed portions of the dielectric cap layer down until reaching the silicon oxide spacer beneath the dielectric cap layer includes using an etch chemistry that is more selective to silicon nitride as compared to silicon oxide.

13. A method of forming self-aligned contacts in a semiconductor device, the method comprising:
receiving a substrate having a first structure of a first material composition and a second structure of a second material composition, the second structure being formed immediately adjacent to the first structure, the first structure and second structure being of different heights such that together the first structure and the second structure defining a first topography that is non-planar at an upper surface thereof;
depositing a first layer on the first topography, the first layer being partially conformal resulting in the first layer defining a second topography, the first layer defining a valley over the first structure and forming a peak over the second structure;
depositing a second layer on the first layer, the second layer filling the defined valley; and
etching portions of the first layer down until reaching the second structure beneath the first layer, the second layer in the defined valley functioning as a hard mask that impedes etching of the first layer above the first structure relative to etching of the first layer above the second structure.

14. A method of forming self-aligned contacts in a semiconductor device, the method comprising:
providing a substrate having a first structure comprising a metal gate electrode and a second structure comprising a silicon oxide spacer, the second structure being formed adjacent to the first structure and having a greater height than the first structure such that together the first structure and the second structure define a first non-planar topography;
depositing a first layer on the first topography, the first layer being partially conformal resulting in the first layer defining a second non-planar topography different than the first non-planar topography, the first layer defining a valley over the first structure and forming a peak over the second structure;
depositing a second layer on the first layer, the second layer being sufficiently thick to fill the defined valley and cover the peak of the second non-planar topography;
planarizing the second layer down to the first layer above the second structure such that the peak in the first layer is exposed while the defined valley remains filled with the second layer; and
etching exposed portions of the first layer down until reaching the second structure beneath the first layer, the second layer in the defined valley functioning as a hard mask that impedes etching of the first layer above the first structure relative to etching of the first layer above the second structure.

15. The method of claim 14 , wherein providing the substrate includes preparing a planarized replacement metal gate (RMG) structure of a gate device on a semiconductor substrate, the RMG structure having the metal gate electrode as the first structure with a side barrier layer, and the silicon oxide spacer being in contact with the side barrier layer, and recessing the first structure to provide the second structure with the greater height.

16. The method of claim 14 , further comprising:
depositing a third layer that fills gaps in the first layer and that covers the first layer.

17. The method of claim 16 , further comprising:
executing a self-aligned contact etch process that etches through the third layer and the second structure.

18. The method of claim 16 , wherein the first layer is a dielectric cap layer, and wherein the second layer and the third layer are silicon oxide layers.

Assignees

• Tokyo Electron Ltd

Inventors

• Metz Andrew

Classifications

• H10W20/071

  of dielectric parts thereof · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D30/6215 Primary

  having multiple independently-addressable gate electrodes · CPC title