Method for forming semiconductor device

Patent metadata

Field	Value
Publication number	US-9780199-B2
Application number	US-201514862165-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A method of forming a semiconductor device includes following steps. Firstly, a gate structure is formed on a substrate, and two source/drain regions are formed. Then, a contact etching stop layer (CESL) is formed to cover the source/drain regions, and a first interlayer dielectric (ILD) layer is formed on the CESL. Next, a replace metal gate process is performed to form a metal gate and a capping layer on the metal gate, and a second ILD layer is formed on the first ILD layer. Following these, a first opening is formed in the second and first ILD layers to partially expose the CESL, and a second opening is formed in the second ILD to expose the capping layer. Finally, the CESL and the capping layer are simultaneously removed.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a gate structure on the substrate, wherein the gate structure has a polysilicon gate;
forming two source/drain regions adjacent to the gate structure;
forming a contact etching stop layer on the substrate, covering the source/drain regions;
forming a first dielectric layer on the contact etching stop layer;
performing a replace metal gate process, to form a metal gate and a capping layer on the metal gate;
forming a second dielectric layer on the first dielectric layer;
forming a preliminary etch mask on the second dielectric layer;
after forming the preliminary etch mask, forming a patterned mask layer on the second dielectric layer;
forming a first opening in the second dielectric layer and the first dielectric layer by using the patterned mask layer, wherein the first opening is formed as two separate portions separated by the masking effect of the preliminary etch mask, and the two separate portions of the first opening to expose portions of the contact etching stop layer on the source/drain regions;
forming a second opening in the second dielectric layer to expose a portion the capping layer; and
simultaneously removing the portion of the contact etching stop layer on the source/drain regions and the portion of the capping layer.

2. The method of forming the semiconductor device according to claim 1 , wherein the forming of the source/drain regions comprises:
forming an epitaxial layer in the substrate adjacent to the gate structure.

3. The method of forming the semiconductor device according to claim 1 , wherein the capping layer and the contact etching stop layer comprises a same material.

4. The method of forming the semiconductor device according to claim 1 , wherein the capping layer and the contact etching stop layer comprise different materials.

5. The method of forming the semiconductor device according to claim 1 , further comprising:
forming another patterned mask layer on the second dielectric layer to fill in the first opening, wherein the second opening is formed by using the another patterned mask layer as a mask.

6. The method of forming the semiconductor device according to claim 1 , further comprising:
performing a silicidation process to form a silicide layer on the source/drain regions in the first opening.

7. The method of forming the semiconductor device according to claim 1 , further comprising:
forming a first plug and a second plug in the first opening and the second opening respectively.

8. The method of forming the semiconductor device according to claim 7 , wherein the first plug and the second plug are formed simultaneously.

9. The method of forming the contact structure according to claim 7 , wherein each of the first plug and the second plug comprises a barrier layer and a contact metal layer.

10. The method of forming the semiconductor device according to claim 7 , wherein the top of the first plug is level with the top of the second plug.

11. The method of forming the semiconductor device according to claim 1 , wherein the top of the capping layer is level with the top of the first dielectric layer.

12. The method of forming the semiconductor device according to claim 1 , further comprising:
removing the slot-cut pattern.

13. The method of forming the semiconductor device according to claim 1 , further comprising:
forming a fin shaped structure in the substrate, wherein the gate structure is formed across the fin shaped structure, and the source/drain regions are formed in the fin shaped structure.

14. The method of forming the semiconductor device according to claim 13 , further comprising:
forming a shallow trench isolation in the substrate and surrounding the fin-shaped structure with the shallow trench isolation.

Assignees

• United Microelectronics Corp

Inventors

• Hung Ching-Wen
• Huang Chih-Sen
• Chen Yi-Wei
• Tzou Shih-Fang

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/66795 Primary

  Electricity · mapped topic