Method of forming a self-aligned contact using selective SiO2 deposition

Patent metadata

Field	Value
Publication number	US-10453749-B2
Application number	US-201815895736-A
Country	US
Kind code	B2
Filing date	Feb 13, 2018
Priority date	Feb 14, 2017
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

First claim

What is claimed is:

1. A substrate processing method, comprising:
providing a planarized substrate containing a dielectric layer surface and a metal-containing surface;
coating the dielectric layer surface with a metal-containing catalyst layer; and
exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO 2 layer on the metal-containing catalyst layer on the dielectric layer surface, wherein the exposing the planarized substrate to the process gas containing the silanol gas is performed in the absence of any oxidizing and hydrolyzing agent at a substrate temperature of approximately 150° C., or less.

2. The method of claim 1 , wherein the SiO 2 layer forms a raised SiO 2 feature adjacent to the metal-containing surface.

3. The method of claim 1 , wherein the silanol gas is selected from the group consisting of tris(tert-pentoxy) silanol, tris(tert-butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.

4. The method of claim 1 , wherein the substrate temperature is approximately 150° C., or less, during the exposing.

5. The method of claim 1 , wherein the substrate temperature is approximately 100° C., or less, during the exposing.

6. The method of claim 1 , wherein the process gas consists of a silanol gas and an inert gas.

7. The method of claim 1 , wherein the SiO 2 layer is deposited on the metal-containing catalyst layer in a self-limiting process.

8. The method of claim 7 , wherein a thickness of the SiO 2 layer is about 5 nm.

9. The method of claim 1 , wherein the exposing further includes
exposing the planarized substrate to the process gas containing the silanol gas for an additional time period that deposits a thinner additional SiO 2 layer on the metal-containing surface; and
removing the additional SiO 2 layer from the metal-containing surface in an etching process.

10. The method of claim 9 , further comprising, repeating the coating, exposing and removing steps at least once in order to increase a thickness of the SiO 2 layer on the dielectric layer surface.

11. The method of claim 1 , further comprising:
depositing an etch stop layer on the SiO 2 layer and on the metal-containing surface.

12. The method of claim 11 , further comprising
depositing an interlayer dielectric layer on the planarized substrate;
etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface; and
filling the recessed feature with a metal.

13. The method of claim 11 , wherein the etch stop layer includes Al 2 O 3 .

14. A substrate processing method, comprising:
providing a planarized substrate containing a dielectric layer surface and a metal-containing surface;
coating the dielectric layer surface with a metal-containing catalyst layer;
exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO 2 layer on the dielectric layer surface relative to the metal-containing surface, wherein the exposing is performed in the absence of any oxidizing and hydrolyzing agent at a substrate temperature of approximately 150° C., or less;
depositing an etch stop layer on the SiO 2 layer and on the metal-containing surface;
depositing an interlayer dielectric layer on the planarized substrate;
etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface; and
filling the recessed feature with a metal.

15. The method of claim 14 , wherein the etch stop layer includes Al 2 O 3 .

16. The method of claim 14 , wherein the SiO 2 layer forms a raised SiO 2 feature adjacent to the metal-containing surface.

17. A substrate processing method, comprising:
providing a planarized substrate containing a dielectric layer surface and a metal-containing surface;
coating the dielectric layer surface with a first metal-containing catalyst layer;
exposing the planarized substrate to a process gas containing a silanol gas for a time period that deposits a SiO 2 layer on the dielectric layer surfaces and a thinner additional SiO 2 layer on the metal-containing surface, wherein the exposing is performed in the absence of any oxidizing and hydrolyzing agent at a substrate temperature of approximately 150° C., or less;
removing the additional SiO 2 layer from the metal-containing surface in an etching process; and
repeating the coating, exposing and removing steps at least once in order to increase a thickness of the SiO 2 layer on the dielectric layer surface.

18. The method of claim 17 , wherein the etch stop layer includes Al 2 O 3 .

19. The method of claim 17 , wherein the SiO 2 layer forms a raised SiO 2 feature adjacent the metal-containing surface.

Assignees

• Tokyo Electron Ltd

Inventors

• Tapily Kandabara N
• Han Sangcheol
• Chae Soo Doo

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6686

  the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane · CPC title

• H10P14/6512

  by exposure to a gas or vapour · CPC title