Integrated circuit device with gate line crossing fin-type active region

Patent metadata

Field	Value
Publication number	US-10043800-B2
Application number	US-201715442859-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Sep 22, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a substrate including a device active region;
a fin-type active region protruding in a first direction from the substrate on the device active region;
a gate line crossing the fin-type active region, the gate line overlapping an upper surface and opposite sidewalls of the fin-type active region;
an insulating spacer disposed on sidewalls of the gate line;
a first source/drain region disposed on the fin-type active region at a first side of the gate line and a second source/drain region disposed on the fin-type active region at a second side of the gate line;
a first conductive plug connected to at least one of the first source/drain region and the second source/drain region; and
a capping layer disposed on the gate line, the capping layer extending substantially parallel to the gate line,
wherein the capping layer includes a first part overlapping the gate line and extending substantially parallel to the gate line, and a second part overlapping the insulating spacer,
wherein the first part and the second part have different compositions with respect to each other, and
wherein the second part contacts the first part and the first conductive plug.

2. The integrated circuit device of claim 1 , wherein the insulating spacer, the first part and the second part have different compositions with respect to each other.

3. The integrated circuit device of claim 1 , wherein the first part includes a first insulating layer having a first dielectric constant, the second part includes a portion of the first insulating layer that is doped, and the insulating spacer includes a second insulating layer having a smaller dielectric constant than the first dielectric constant.

4. The integrated circuit device of claim 1 , wherein, when the first part includes a first insulating layer having a first dielectric constant, the insulating spacer includes a second insulating layer having a smaller dielectric constant than the first insulating layer, and the second part includes a portion of the second insulating layer that is doped.

5. The integrated circuit device of claim 1 , wherein the capping layer further includes a third part disposed between the gate line and the first part and between the insulating spacer and the second part,
wherein the third part extends substantially parallel to the gate line and includes a third insulating layer having a same composition as the composition of the first part.

6. The integrated circuit device of claim 1 , wherein the first part contacts the gate line and the insulating spacer.

7. The integrated circuit device of claim 1 , wherein, in the first direction, an upper surface of the first conductive plug is disposed closer to a surface of the substrate from which the fin-type active region protrudes than an upper surface of the second part.

8. The integrated circuit device of claim 1 , further comprising a second conductive plug penetrating the capping layer on the device active region,
wherein the second conductive plug is connected to the gate line, and
wherein, in the first direction, an upper surface of the second conductive plug is disposed farther from a surface of the substrate from which the fin-type active region protrudes than an upper surface of the first conductive plug.

9. The integrated circuit device of claim 8 , wherein the second part is interposed between the first conductive plug and the second conductive plug.

10. The integrated circuit device of claim 8 , further comprising:
an insulating liner covering the capping layer and the first conductive plug, the insulating liner including a pocket portion protruding toward the substrate to contact the upper surface of the first conductive plug, wherein the pocket portion delimits a pocket region that overlaps the first conductive plug; and
a pocket insulating layer filling the pocket region,
wherein the insulating liner and the pocket insulating layer include different materials with respect to each other.

11. An integrated circuit device, comprising:
a substrate including a device active region;
a plurality of fin-type active regions protruding in a first direction from the substrate on the device active region, the plurality of fin-type active regions extending in a second direction perpendicular to the first direction;
a plurality of gate lines disposed on the plurality of fin-type active regions, the plurality of gate lines extending in a third direction crossing the second direction and perpendicular to the first direction;
a plurality of insulating spacers disposed on opposite sidewalls of respective gate lines of the plurality of gate lines;
a plurality of source and drain regions disposed on the plurality of fin-type active regions, wherein pairs of source and drain regions are disposed at opposite sides of respective gate lines of the plurality of gate lines;
a first conductive plug connected to at least one pair of the plurality of source and drain regions between two adjacent gate lines of the plurality of gate lines;
a plurality of first capping layers overlapping the plurality of gate lines, the plurality of first capping layers extending parallel to the plurality of gate lines; and
at least one second capping layer overlapping at least one of the plurality of insulating spacers, the at least one second capping layer contacting at least one of the plurality of first capping layers and the first conductive plug, and
wherein the plurality of first capping layers and the at least one second capping layer have different compositions with respect to each other.

12. The integrated circuit device of claim 11 , wherein a plurality of second capping layers overlap the plurality of insulating spacers and extend substantially parallel to the plurality of gate lines, and
wherein the first conductive plug contacts two adjacent second capping layers of the plurality of second capping layers.

13. The integrated circuit device of claim 11 , wherein a pair of the second capping layers are disposed between a pair of adjacent gate lines,
wherein the pair of second capping layers are disposed on opposite sides of the first conductive plug.

14. The integrated circuit device of claim 11 , further comprising a plurality of third capping layers, wherein at least one of the third capping layers is interposed between a pair of the first capping layers of the plurality of first capping layers, and overlaps a respective gate line of the plurality of gate lines, wherein the plurality of the third capping layers extend parallel to the plurality of gate lines,
wherein the plurality of the third capping layers and the plurality of the first capping layers include a same insulating material, and
wherein a first gate line of the plurality of gate lines is spaced apart from the at least one of the second capping layers by at least one of the plurality of the third capping layers.

15. The integrated circuit device of claim 11 , further comprising:
an inter-gate insulating layer covering at least one pair of the plurality of source and drain regions on the device active region; and
an inter-gate capping layer disposed on the inter-gate insulating layer, the inter-gate capping layer overlapping the at least one pair of the plurality of source and drain regions and contacting the inter-gate insulating layer and the at least one second capping layer.

16. An integrated circuit device, comprising:
a substrate including a device active region;
a fin-type active region protruding in a first direction from the substrate on the device active regi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Changhwa
• Choi Kyungin
• Jun Hwichan
• Hwang Inchan

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P14/6548

  by forming intermediate materials, e.g. capping layers or diffusion barriers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title