Structure and method to self align via to top and bottom of tight pitch metal interconnect layers

US10553532B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10553532-B2
Application numberUS-201415529484-A
CountryUS
Kind codeB2
Filing dateDec 24, 2014
Priority dateDec 24, 2014
Publication dateFeb 4, 2020
Grant dateFeb 4, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.

First claim

Opening claim text (preview).

What is claimed is: 1. An interconnect structure comprising: an interlayer dielectric (ILD) with a top surface and a bottom surface: first interconnect lines in the ILD, wherein a top surface of each of the first interconnect lines is recessed below the top surface of the ILD, and wherein a bottom surface of each of the first interconnect lines is above the bottom surface of the ILD; second interconnect lines in the ILD arranged in an alternating pattern with the first interconnect lines, wherein a top surface of each of the second interconnect lines is recessed below the top surface of the ILD and wherein a bottom surface of each of the second interconnect lines is above the bottom surface of the ILD; and a self-aligned overhead via over one or more of the first interconnect lines or over one or more of the second interconnect lines, wherein the self-aligned overhead via includes a top surface that is substantially coplanar with a top surface of the ILD. 2. The interconnect structure of claim 1 , further comprising one or more self-aligned through vias below one or more of the first interconnect lines or below one or more of the second interconnect lines. 3. The interconnect structure of claim 1 , wherein a dielectric cap is formed over first and second interconnect lines that do not have a self-aligned overhead via formed over them. 4. The interconnect structure of claim 3 , wherein the dielectric caps are a SiO x C y N z material, a metal oxide material, or a metal nitride material. 5. The interconnect structure of claim 1 , wherein the self-aligned overhead via includes a notch. 6. The interconnect structure of claim 5 , further comprising a contact metal formed over the top surface of the overhead via. 7. The interconnect structure of claim 6 , wherein the contact metal is a different material than the overhead via. 8. The interconnect structure of claim 1 , wherein an air gap is formed in a space between one or more of the first interconnect lines and the second interconnect lines. 9. The interconnect structure of claim 8 , wherein the air gap extends along at least half the height of the sidewalls of the first and second interconnect lines. 10. The interconnect structure of claim 8 , wherein the air gap extends along the entire height of the sidewalls of the first and second interconnect lines. 11. The interconnect structure of claim 1 , wherein the first and second interconnect lines have a height to width ratio that is 2:1 or greater. 12. The interconnect structure of claim 1 , wherein the first interconnect lines are spaced less than 30 nm from the second interconnect lines. 13. A method of forming an interconnect structure comprising: forming a plurality of first trenches into an interlayer dielectric (ILD); disposing a first metal into the first trenches to form first interconnect lines and first self-aligned overhead vias over the first interconnect lines; removing one or more of the first self-aligned vias to expose top surfaces of one or more of the first interconnect lines; forming first dielectric caps above the exposed top surfaces of the first interconnect lines; forming a plurality second trenches into the ILD in an alternating pattern with the first trenches; disposing a second metal into the second trenches to form second interconnect lines and second self-aligned overhead vias; removing one or more of the second self-aligned overhead vias to expose top surfaces of one or more of the second interconnect lines; and forming second dielectric caps above exposed top surfaces of the second interconnect lines. 14. The method of claim 13 , wherein forming the first trenches comprises: forming a backbone layer above a first hardmask layer formed over the ILD; forming spacers on the backbone layer, wherein a portion of the first hardmask layer remains exposed between the spacers; and etching through the exposed portions of the first hardmask layer and into the ILD underneath the exposed portions of the first hardmask layer. 15. The method of claim 14 , wherein forming the second trench comprises: etching through the backbone layer; and etching through portions of the first hardmask layer and into the ILD. 16. The method of claim 15 , further comprising: etching through portions of the ILD underneath one or more of the first trenches to form one or more first through via openings prior to disposing the first metal into the first trenches, and wherein disposing the first metal into the first trenches further includes forming first self aligned through vias in the first through via openings. 17. The method of claim 15 , further comprising: etching through portions of the ILD underneath one or more of the second trenches to form second through via openings prior to disposing the second metal into the second trenches, and wherein disposing the second metal into the second trenches further includes forming second self-aligned through vias in the second through via openings. 18. The method of claim 13 , wherein the first and second interconnect lines have a height to width ratio that is 2:1 or greater. 19. The method of claim 13 , further comprising: removing the ILD from between one or more of the first interconnect lines and the second interconnect lines; and disposing an ILD fill material onto the interconnect structure that does not fill the space proximate to sidewalls of the first interconnect lines and the second interconnect lines. 20. The method of claim 19 , wherein the sidewalls of the first interconnect lines and the second interconnect lines are not contacted by the ILD or the ILD fill material. 21. The method of claim 13 , wherein the first interconnect lines are spaced apart from the second interconnect lines by less than 30 nm. 22. The method of claim 13 , wherein the dielectric caps are a SiO x C y N z material, a metal oxide material, or a metal nitride material. 23. A method of forming an interconnect structure comprising: forming a backbone layer above a first hardmask layer formed over an ILD; forming spacers on the backbone layer, wherein a portion of the first hardmask layer remains exposed between the spacers; etching through the exposed portions of the first hardmask layer and into the ILD underneath the exposed portions of the first hardmask layer to form a plurality of first trenches into the interlayer dielectric (ILD); disposing a first metal into the first trenches to form first interconnect lines and first self aligned overhead vias over the first interconnect lines; removing one or more of the first self-aligned vias to expose a top surface of one or more of the first interconnect lines; forming first dielectric caps above the exposed top surfaces of the first interconnect lines; etching through the backbone layer; etching through portions of the first hardmask layer and into the ILD to forming one or more second trenches into the ILD in an alternating pattern with the first trenches wherein the first trenches are spaced apart from the second trenches by less than 30 nm; disposing a second metal into the one or more second trenches to form second interconnect lines and second self-aligned overhead vias; removing one or more of the second self-aligned overhead vias to expose a top surface of one or more of the second interconnect lines; and forming second dielectric caps above exposed top surfaces of the second interconnect lines. 24. The method of claim

Assignees

Inventors

Classifications

  • by forming self-aligned vias · CPC title

  • characterised by the processes involved to create the masks · CPC title

  • using masks for insulating materials · CPC title

  • Cross-sectional shapes or dispositions of interconnections · CPC title

  • using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

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What does patent US10553532B2 cover?
Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/069. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 04 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).