Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice

Patent metadata

Field	Value
Publication number	US-11742202-B2
Application number	US-202217653319-A
Country	US
Kind code	B2
Filing date	Mar 3, 2022
Priority date	Mar 3, 2021
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers including stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The method may further include forming a body above the RF ground plane layer, forming spaced apart source and drain regions adjacent the body and defining a channel region in the body, and forming a gate overlying the channel region.

First claim

The invention claimed is:

1. A method for making a radio frequency (RF) semiconductor device comprising:
forming an RF ground plane layer on a semiconductor-on-insulator substrate and comprising a conductive superlattice, the conductive superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions;
forming a body above the RF ground plane layer;
forming spaced apart source and drain regions adjacent the body and defining a channel region in the body; and
forming a gate overlying the channel region.

2. The method of claim 1 wherein the RF semiconductor device comprises an RF switch.

3. The method of claim 1 comprising forming a body contact coupled to the body and the RF ground plane layer.

4. The method of claim 3 wherein the body contact comprises first and second body contact portions adjacent opposite ends of the channel region.

5. The method of claim 1 wherein the RF ground plane has a thickness in a range of 10-50 nm.

6. The method of claim 1 wherein the doped base semiconductor portions have a dopant concentration of at least 5×10 17 cm −3 .

7. The method of claim 1 wherein forming the gate comprises forming a gate insulator over the channel region, and forming a gate electrode over the gate insulator.

8. The method of claim 1 wherein the doped base semiconductor monolayers comprise silicon.

9. The method of claim 1 wherein the non-semiconductor monolayers comprise oxygen.

10. The method of claim 1 wherein the semiconductor-on-insulator substrate comprises a silicon-on-insulator (SOI) substrate.

11. A method for making a radio frequency (RF) semiconductor device comprising:
a silicon-on-insulator (SOI) substrate;
forming an RF ground plane layer on a silicon-on-insulator (SOI) substrate comprising a conductive superlattice, the conductive superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked doped base silicon monolayers defining a doped base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent doped base silicon portions;
forming a body above the RF ground plane layer;
forming spaced apart source and drain regions adjacent the body and defining a channel region in the body; and
forming a gate overlying the channel region.

12. The method of claim 11 wherein the RF semiconductor device comprises an RF switch.

13. The method of claim 11 further comprising forming a body contact coupled to the body and the RF ground plane layer.

14. The method of claim 13 wherein the body contact comprises first and second body contact portions adjacent opposite ends of the channel region.

15. The method of claim 11 wherein the RF ground plane has a thickness in a range of 10-50 nm.

16. The method of claim 11 wherein the doped base semiconductor portions have a dopant concentration of at least 5×10 17 cm −3 .

17. The method of claim 11 wherein forming the gate comprises forming a gate insulator over the channel region, and forming a gate electrode over the gate insulator.

18. A method for making a radio frequency (RF) switch comprising:
forming an RF ground plane layer on a semiconductor-on-insulator substrate comprising a conductive superlattice, the conductive superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions;
forming a body above the RF ground plane layer;
forming a body contact coupled to the body and the RF ground plane layer;
forming spaced apart source and drain regions adjacent the body and defining a channel region in the body; and
forming a gate overlying the channel region for controlling charge carrier flow through the channel region responsive to an RF switching control signal.

19. The method of claim 18 wherein the body contact comprises first and second body contact portions adjacent opposite ends of the channel region.

20. The method of claim 18 wherein the RF ground plane has a thickness in a range of 10-50 nm.

21. The method of claim 18 wherein the doped base semiconductor portions have a dopant concentration of at least 5×10 17 cm −3 .

22. The method of claim 18 wherein forming the gate comprises forming a gate insulator over the channel region, and forming a gate electrode over the gate insulator.

23. The method of claim 18 wherein the doped base semiconductor monolayers comprise silicon, and the non-semiconductor monolayers comprise oxygen.

Assignees

• Atomera Inc

Inventors

• Takeuchi Hideki
• Mears Robert J

Classifications

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3252 Primary

  Alternating layers, e.g. superlattice · CPC title

• H10D62/8164

  comprising only semiconductor materials  (potential variation in long-range structurally-disordered materials H10D62/8163) · CPC title

• H10D30/751

  having composition variations in the channel regions · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title