Semiconductor device including a superlattice and replacement metal gate structure and related methods

Patent metadata

Field	Value
Publication number	US-10084045-B2
Application number	US-201715633918-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Nov 25, 2014
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

First claim

That which is claimed is:

1. A semiconductor device comprising:
a substrate having a channel recess therein;
a plurality of spaced apart shallow trench isolation (STI) regions in said substrate;
source and drain regions spaced apart in the substrate and between a pair of the STI regions; and
a superlattice channel in the channel recess of said substrate extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a replacement gate over the superlattice channel having lateral edges vertically aligned with lateral edges of the superlattice channel.

2. The semiconductor device of claim 1 further comprising a well implant in the substrate between the pair of STI regions.

3. The semiconductor device of claim 1 wherein the replacement gate comprises:
a high K dielectric layer over the superlattice channel; and
a metal gate electrode over the high K dielectric layer.

4. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

5. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

6. The semiconductor device of claim 1 wherein the at least one non-semiconductor layer comprises oxygen.

7. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

8. The semiconductor device of claim 1 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

9. The semiconductor device of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.

10. A semiconductor device comprising:
a substrate having a channel recess therein;
a plurality of spaced apart shallow trench isolation (STI) regions in said substrate;
source and drain regions spaced apart in the substrate and between a pair of the STI regions;
a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and
a replacement gate comprising a high K dielectric layer over the superlattice channel and a metal gate electrode over the high K dielectric layer, the replacement gate having lateral edges vertically aligned with lateral edges of the superlattice channel.

11. The semiconductor device of claim 10 further comprising a well implant in the substrate between the pair of STI regions.

12. The semiconductor device of claim 10 wherein the superlattice channel further comprises a base silicon cap layer on an uppermost group of layers.

13. The semiconductor device of claim 10 wherein at least some semiconductor atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

14. A semiconductor device comprising:
a substrate;
a pair of spaced apart isolation regions in said substrate;
source and drain regions spaced apart in the substrate and between the pair of the isolation regions;
the substrate having a channel recess extending between the source and drain regions;
a superlattice channel in the channel recess and contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a gate over the superlattice channel comprising a dielectric layer and a metal gate electrode thereon, the gate having lateral edges vertically aligned with lateral edges of the superlattice channel.

15. The semiconductor device of claim 14 further comprising a well implant in the substrate between the pair of isolation regions.

16. The semiconductor device of claim 14 wherein the dielectric layer comprises a high K dielectric layer.

17. The semiconductor device of claim 14 wherein each base semiconductor portion comprises silicon.

18. The semiconductor device of claim 14 wherein each base semiconductor portion comprises germanium.

19. The semiconductor device of claim 14 wherein the at least one non-semiconductor layer comprises oxygen.

20. The semiconductor device of claim 14 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

21. The semiconductor device of claim 14 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

22. The semiconductor device of claim 14 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.

Assignees

• Atomera Inc

Inventors

• Mears Robert J
• King Liu Tsu-Jae
• Takeuchi Hideki

Classifications

• H01L29/1083

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/154 Primary

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic

• H01L29/66431

  Electricity · mapped topic