Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source

Patent metadata

Field	Value
Publication number	US-9558939-B1
Application number	US-201614996312-A
Country	US
Kind code	B1
Filing date	Jan 15, 2016
Priority date	Jan 15, 2016
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A method for making a semiconductor device may include forming a plurality of spaced apart structures on a semiconductor substrate within a semiconductor processing chamber, with each structure including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Furthermore, the oxygen monolayers may be formed using N 2 O as an oxygen source.

First claim

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming a plurality of spaced apart structures on a semiconductor substrate within a semiconductor processing chamber, each structure comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
wherein the oxygen monolayers are formed using N 2 O as an oxygen source.

2. The method of claim 1 wherein forming comprises forming the plurality of groups of spaced apart structures using epitaxial chemical vapor deposition (CVD).

3. The method of claim 1 wherein the base silicon monolayers are formed at a temperature in a range of 600° C. to 800° C.

4. The method of claim 3 wherein the base silicon monolayers are formed at a temperature in a range of 665° C. to 685° C.

5. The method of claim 1 wherein the oxygen monolayers are formed at a temperature in a range of 500° C. to 750° C.

6. The method of claim 1 wherein an exposure time for the oxygen source is between 1 and 240 seconds.

7. The method of claim 1 wherein the oxygen source comprises a helium source gas with less than 2% N 2 O.

8. The method of claim 1 further comprising forming shallow trench isolation (STI) regions between the spaced apart structures.

9. The method of claim 8 wherein the STI regions are formed prior to forming the spaced apart structures.

10. The method of claim 1 further comprising forming a respective cap semiconductor layer on each of the spaced apart structures.

11. The method of claim 10 wherein forming the cap semiconductor layers comprises forming the cap semiconductor layers at a temperature in a range of 580° C. to 900° C.

12. A method for making a semiconductor device comprising:
forming a plurality of spaced apart structures on a semiconductor substrate with shallow trench isolation (STI) regions between adjacent structures within a semiconductor processing chamber using epitaxial chemical vapor deposition (CVD), each structure comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
wherein the oxygen monolayers are formed using N 2 O as an oxygen source.

13. The method of claim 12 wherein the base silicon monolayers are formed at a temperature in a range of 600° C. to 800° C.

14. The method of claim 13 wherein the base silicon monolayers are formed at a temperature in a range of 665° C. to 685° C.

15. The method of claim 12 wherein the oxygen monolayers are formed at a temperature in a range of 500° C. to 750° C.

16. The method of claim 12 wherein an exposure time for the oxygen source is between 1 and 240 seconds.

17. The method of claim 12 wherein the oxygen source comprises a helium source gas with less than 2% N 2 O.

18. The method of claim 12 wherein the STI regions are formed prior to forming the spaced apart structures.

19. The method of claim 12 further comprising forming a respective cap semiconductor layer on each of the spaced apart structures.

20. The method of claim 12 wherein forming the cap semiconductor layers comprises forming the cap semiconductor layers at a temperature in a range of 580° C. to 900° C.

21. A method for making a semiconductor device comprising:
forming a plurality of spaced apart structures on a semiconductor substrate within a semiconductor processing chamber, each structure comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
wherein the oxygen monolayers are formed using N 2 O as an oxygen source at a temperature in a range of 500° C. to 750° C., and wherein the base silicon monolayers are formed at a temperature in a range of 600° C. to 800° C.

22. The method of claim 21 wherein forming comprises forming the plurality of groups of spaced apart structures using epitaxial chemical vapor deposition (CVD).

23. The method of claim 21 wherein the base silicon monolayers are formed at a temperature in a range of 665° C. to 685° C.

24. The method of claim 21 wherein an exposure time for the oxygen source is between 1 and 240 seconds.

25. The method of claim 21 wherein the oxygen source comprises a helium source gas with less than 2% N 2 O.

Assignees

• Atomera Inc

Inventors

• Stephenson Robert
• Cody Nyles

Classifications

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3252 Primary

  Alternating layers, e.g. superlattice · CPC title

• H10D62/815 Primary

  of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] · CPC title