Semiconductor device including threshold voltage measurement circuitry

Patent metadata

Field	Value
Publication number	US-10107854-B2
Application number	US-201715678616-A
Country	US
Kind code	B2
Filing date	Aug 16, 2017
Priority date	Aug 17, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.

First claim

That which is claimed is:

1. A semiconductor device comprising:
a substrate;
active circuitry on the substrate and comprising a plurality of differential transistor pairs; and
threshold voltage test circuitry on the substrate and comprising
a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, each test transistor having a respective input and output, and
at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof;

wherein the plurality of differential transistor pairs and the pair of differential test transistors each comprises spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region;
wherein each of the channel regions comprises a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions.

2. The semiconductor device of claim 1 wherein the at least one gain stage comprises a plurality of gain stages configured to successively amplify the difference between the outputs of the differential test transistors over an input voltage range.

3. The semiconductor device of claim 1 wherein the semiconductor substrate comprises a semiconductor wafer; wherein the active circuitry comprises a plurality of spaced apart active circuitry areas separated by scribe lines; and wherein the threshold voltage test circuitry is positioned within at least one of the scribe lines.

4. The semiconductor device of claim 1 wherein the active circuitry comprises at least one memory cell array.

5. The semiconductor device of claim 1 wherein the at least one gain stage comprises a sense amplifier coupled to first conduction terminals of the pair of differential test transistors, and a current source coupled to second conduction terminals of the pair of differential test transistors.

6. The semiconductor device of claim 1 wherein the pair of differential test transistors comprises a pair of NMOS differential test transistors.

7. The semiconductor device of claim 1 wherein the pair of differential test transistors comprises a pair of PMOS differential test transistors.

8. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

9. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

10. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

11. The semiconductor device of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions of each superlattice layer are chemically bound together through the non-semiconductor layer therebetween.

12. A semiconductor device comprising:
a semiconductor wafer;
a plurality of active circuitry areas spaced apart on the semiconductor wafer by scribe lines therebetween, each active circuitry area comprising a plurality of differential transistor pairs; and
threshold voltage test circuitry on the substrate within at least one of the scribe lines and comprising
a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, each test transistor having a respective input and output, and
a plurality of gain stages configured to successively amplify the difference between the outputs of the differential test transistors over an input voltage range for measuring a threshold voltage thereof;

wherein the plurality of differential transistor pairs and the pair of differential test transistors each comprises spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region;
wherein each of the channel regions comprises a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions.

13. The semiconductor device of claim 12 wherein each active circuitry area comprises a memory cell array.

14. The semiconductor device of claim 12 wherein a first one of the plurality of gain stages comprises a sense amplifier coupled to first conduction terminals of the pair of differential test transistors, and a current source coupled to second conduction terminals of the pair of differential test transistors.

15. The semiconductor device of claim 12 wherein the pair of differential test transistors comprises a pair of NMOS differential test transistors.

16. The semiconductor device of claim 12 wherein the pair of differential test transistors comprises a pair of PMOS differential test transistors.

17. A semiconductor device comprising:
a substrate;
active circuitry on the substrate and comprising a plurality of differential transistor pairs; and
threshold voltage test circuitry on the substrate and comprising
a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, each test transistor having a respective input and output, and
at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof;

wherein the plurality of differential transistor pairs and the pair of differential test transistors each comprises spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region;
wherein each of the channel regions comprises a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor silicon and at least one oxygen monolayer thereon constrained within a crystal lattice of adjacent base silicon portions.

18. The semiconductor device of claim 17 wherein the at least one gain stage comprises a plurality of gain stages configured to successively amplify the difference between the outputs of the differential test transistors over an input voltage range.

19. The semiconductor device of claim 17 wherein the semiconductor substrate comprises a semiconductor wafer; wherein the active circuitry comprises a plurality of spaced apart active circuitry areas separated by scribe lines; and wherein the threshold voltage test circuitry is positioned within at least one of the scribe lines.

20. The semiconductor device of claim 17 wherein the active circuitry comprises at least one memory cell array.

21. The semiconductor device of claim 17 wherein the at least one gain stage comprises a sense amplifier coupled to first conduction terminals of the pair of differential test transistors, and a current source coupled to second conduction terminals of the pair of differential test transistors.

Assignees

• Atomera Inc

Inventors

• Roy Richard Stephen

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G01R31/31932

  Comparators · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• H03F2203/45361

  the AAC comprising multiple transistors parallel coupled at their drains only, e.g. in a cascode dif amp, only those forming the composite common source transistor · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title