Semiconductor devices with enhanced deterministic doping and related methods
US-2017294514-A1 · Oct 12, 2017 · US
Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers
US10170604B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10170604-B2 |
| Application number | US-201715670274-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 7, 2017 |
| Priority date | Aug 8, 2016 |
| Publication date | Jan 1, 2019 |
| Grant date | Jan 1, 2019 |
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Abstract
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A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.
First claim
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That which is claimed is: 1. A method for making a semiconductor device comprising: forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, forming a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and comprising a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, forming a second intrinsic semiconductor layer on the second barrier layer, forming a third barrier layer on the second intrinsic semiconductor layer and comprising a third superlattice, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer. 2. The method of claim 1 wherein the first and second doped semiconductor layers each comprises silicon, and wherein the second intrinsic layer comprises at least one of silicon and germanium. 3. The method of claim 1 wherein the fourth barrier layer comprises a fourth superlattice, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. 4. The method of claim 3 wherein the second doped semiconductor layer comprises a single crystal semiconductor layer. 5. The method of claim 1 wherein the first and second doped semiconductor layers have a same dopant conductivity type. 6. The method of claim 1 wherein the first and second doped semiconductor layers have opposite dopant conductivity types. 7. The method of claim 1 wherein the first barrier layer and the first intrinsic semiconductor layer define an electron mean free path control layer. 8. The method of claim 1 wherein the third intrinsic semiconductor layer and the fourth barrier layer define an electron mean free path control layer. 9. The method of claim 1 wherein the respective at least one non-semiconductor monolayer in each of the first, second and third superlattices comprises oxygen. 10. The method of claim 1 wherein the respective semiconductor monolayers in each of the first, second and third superlattices comprise silicon. 11. A method for making a semiconductor device comprising: forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, forming a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and comprising a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, forming a second intrinsic semiconductor layer on the second barrier layer, forming a third barrier layer on the second intrinsic semiconductor layer and comprising a third superlattice, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer, the first and second doped semiconductor layers having the same dopant conductivity type. 12. The method of claim 11 wherein the first and second doped semiconductor layers each comprises silicon, and wherein the second intrinsic layer comprises at least one of silicon and germanium. 13. The method of claim 11 wherein the fourth barrier layer comprises a fourth superlattice, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. 14. The method of claim 13 wherein the second doped semiconductor layer comprises a single crystal semiconductor layer. 15. The method of claim 11 wherein the first barrier layer and the first intrinsic semiconductor layer define a first electron mean free path control layer; and wherein the third intrinsic semiconductor layer and the fourth barrier layer define a second electron mean free path control layer. 16. A method for making a semiconductor device comprising: forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, forming a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and comprising a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, forming a second intrinsic semiconductor layer on the second barrier layer, forming a third barrier layer on the second intrinsic semiconductor layer and also comprisi
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L29/7376Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US10170604B2 cover?
- A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second …
- Who is the assignee on this patent?
- Atomera Inc
- What technology area does this patent fall under?
- Primary CPC classification H01L29/7376. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).