Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods

Patent metadata

Field	Value
Publication number	US-9899479-B2
Application number	US-201615154296-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	May 15, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.

First claim

That which is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate; and
a plurality of field effect transistors (FETs) on the semiconductor substrate and each comprising
a gate,
spaced apart source and drain regions on opposite sides of the gate,
upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions,
a halo implant having a peak halo dopant concentration of at least 1×10 19 atoms/cm 3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, and
a second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×10 19 atoms/cm 3 .

2. The semiconductor device of claim 1 wherein the upper and lower superlattice layers each comprises a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

3. The semiconductor device of claim 2 wherein each base semiconductor portion comprises silicon.

4. The semiconductor device of claim 2 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

5. The semiconductor device of claim 2 wherein the at least one non-semiconductor layer comprises oxygen.

6. The semiconductor device of claim 1 wherein the plurality of FETs comprises a plurality of planar CMOS transistors.

7. The semiconductor device of claim 1 wherein the channel of each of the FETs is further defined in at least a portion of the upper superlattice layer.

8. The semiconductor device of claim 1 wherein each gate comprises a gate oxide layer above the upper superlattice layer, and a gate electrode on the gate oxide layer.

9. A semiconductor device comprising:
a semiconductor substrate; and
a plurality of CMOS transistors on the semiconductor substrate and each comprising
a gate,
spaced apart source and drain regions on opposite sides of the gate,
upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions,
a halo implant having a peak halo dopant concentration of at least 1×10 19 atoms/cm 3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, and
a second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×10 19 atoms/cm 3 ;

the upper and lower superlattice layers each comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

10. The semiconductor device of claim 9 wherein each base semiconductor portion comprises silicon.

11. The semiconductor device of claim 9 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

12. The semiconductor device of claim 9 wherein the at least one non-semiconductor layer comprises oxygen.

13. The semiconductor device of claim 9 wherein the plurality of CMOS transistors comprises a plurality of planar CMOS transistors.

14. The semiconductor device of claim 9 wherein the channel of each of the CMOS transistors is further defined in at least a portion of the upper superlattice layer.

15. The semiconductor device of claim 9 wherein each gate comprises a gate oxide layer above the upper superlattice layer, and a gate electrode on the gate oxide layer.

16. A method of making a semiconductor device comprising:
forming a plurality of field effect transistors (FETs) on a semiconductor substrate, each comprising
a gate,
spaced apart source and drain regions on opposite sides of the gate,
upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions,
a halo implant having a peak halo dopant concentration of at least 1×10 19 atoms/cm 3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, and
a second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×10 19 atoms/cm 3 .

17. The method of claim 16 wherein the upper and lower superlattice layers each comprises a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

18. The method of claim 17 wherein each base semiconductor portion comprises silicon.

19. The method of claim 17 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

20. The method of claim 17 wherein the at least one non-semiconductor layer comprises oxygen.

21. The method of claim 16 wherein forming the plurality of FETs comprises forming a plurality of planar CMOS transistors.

Assignees

• Atomera Inc
• Atomera Inc

Inventors

• Mears Robert J
• Takeuchi Hideki

Classifications

• H01L29/155

  Electricity · mapped topic

• H01L29/0638

  Electricity · mapped topic

• H01L29/152

  Electricity · mapped topic

• H01L29/158

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic