Vertical semiconductor devices including superlattice punch through stop layer and related methods

Patent metadata

Field	Value
Publication number	US-9972685-B2
Application number	US-201514958447-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Nov 22, 2013
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.

First claim

That which is claimed is:

1. A semiconductor device comprising:
a substrate;
a plurality of fins spaced apart on said substrate, each of said fins comprising
a lower semiconductor fin portion extending vertically upward from the substrate,
a plurality of spaced apart superlattice punch-through stop layers on the lower fin portion, each superlattice punch-through stop layer including a plurality of stacked groups of layers, each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
a respective bulk semiconductor layer between adjacent superlattice punch-through stop layers, and
an upper semiconductor fin portion on an uppermost one of said superlattice punch-through stop layers and extending vertically upward therefrom;

source and drain regions at opposing ends of the fins; and
a gate overlying the fins.

2. The semiconductor device of claim 1 further comprising an insulating layer on the substrate surrounding the lower semiconductor fin portions.

3. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

4. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

5. The semiconductor device of claim 1 wherein the at least one non-semiconductor layer comprises oxygen.

6. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

7. The semiconductor device of claim 1 wherein the gate comprises an oxide layer overlying the superlattice channel and a gate electrode overlying the oxide layer.

8. The semiconductor device of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

9. A semiconductor device comprising:
a substrate;
a plurality of fins spaced apart on said substrate, each of said fins comprising
a lower semiconductor fin portion extending vertically upward from the substrate,
a plurality of spaced apart superlattice punch-through stop layers on the lower fin portion, each superlattice punch-through stop layer including a plurality of stacked groups of layers, each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions,
a respective bulk semiconductor layer between adjacent superlattice punch-through stop layers, and
an upper semiconductor fin portion on an uppermost one of said superlattice punch-through stop layers and extending vertically upward therefrom;

source and drain regions at opposing ends of the fins; and
a gate overlying the fins.

10. The semiconductor device of claim 9 further comprising an insulating layer on the substrate surrounding the lower semiconductor fin portions.

11. A semiconductor device comprising:
a substrate;
a plurality of fins spaced apart on said substrate, each of said fins comprising
a lower semiconductor fin portion extending vertically upward from the substrate,
a plurality of spaced apart superlattice punch-through stop layers on the lower fin portion, each superlattice punch-through stop layer including a plurality of stacked groups of layers, each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base germanium monolayers defining a base germanium portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base germanium portions, with the at least one non-semiconductor monolayer comprising a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen,
a respective bulk semiconductor layer between adjacent superlattice punch-through stop layers, and
an upper semiconductor fin portion on an uppermost one of said superlattice punch-through stop layers and extending vertically upward therefrom;
source and drain regions at opposing ends of the fins; and
a gate overlying the fins.

12. The semiconductor device of claim 11 further comprising an insulating layer on the substrate surrounding the lower semiconductor fin portions.

Assignees

• Atomera Inc

Inventors

• Mears Robert
• Takeuchi Hideki
• Trautmann Erwin

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10D62/8162 Primary

  having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation · CPC title

• H01L29/0638

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L21/823412

  Electricity · mapped topic