Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods

Patent metadata

Field	Value
Publication number	US-10109342-B2
Application number	US-201715592464-A
Country	US
Kind code	B2
Filing date	May 11, 2017
Priority date	May 11, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.

First claim

That which is claimed is:

1. A semiconductor device comprising:
a plurality of volatile memory cells;
peripheral circuitry coupled to the plurality of volatile memory cells and comprising a plurality of low threshold voltage (Vt) transistors configured to provide high speed operation during a first operating mode and a plurality of high Vt transistors configured as headers to reduce leakage in the low Vt transistors during a second operating mode, the high Vt and low Vt transistors each comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during the first operating mode; and
a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during the second operating mode;
wherein the peripheral circuitry is operable at a first clock rate during the first operating mode and a second clock rate lower than the first clock rate during the second operating mode, and wherein data stored in the plurality of volatile memory cells is fully refreshed during the second operating mode.

2. The semiconductor device of claim 1 wherein the first operating mode comprises an active mode, and wherein the second operating mode comprises a standby mode.

3. The semiconductor device of claim 1 wherein the peripheral circuitry comprises a sense amplifier.

4. The semiconductor device of claim 1 wherein the peripheral circuitry comprises a main wordline decoder (MWD) circuit.

5. The semiconductor device of claim 4 wherein the peripheral circuitry further comprises a wordline pre-decoder circuit coupled to the MWD circuitry.

6. The semiconductor device of claim 1 wherein the peripheral circuitry comprises an address decoder circuit.

7. The semiconductor device of claim 1 wherein each of the high Vt and low Vt transistors comprises a source and a drain, and wherein the superlattice defines a channel between the source and the drain.

8. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

9. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

10. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

11. The semiconductor device of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions of each superlattice layer are chemically bound together through the non-semiconductor layer therebetween.

12. A semiconductor device comprising:
a plurality of volatile memory cells;
peripheral circuitry coupled to the plurality of volatile memory cells and comprising a plurality of low threshold voltage (Vt) transistors configured to provide high speed operation during an active mode and a plurality of high Vt transistors configured as headers to reduce leakage in the low Vt transistors during a standby mode, the high Vt and low Vt transistors each comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during the active mode; and
a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply the standby mode;
wherein the peripheral circuitry comprises a sense amplifier;
wherein the peripheral circuit circuitry is operable at a first clock rate during the first operating mode and a second clock rate lower than the first clock rate during the second operating mode, and wherein data stored in the plurality of volatile memory cells is fully refreshed during the second operating mode.

13. The semiconductor device of claim 12 wherein the peripheral circuitry further comprises a main wordline decoder (MWD) circuit.

14. The semiconductor device of claim 13 wherein the peripheral circuitry further comprises a wordline pre-decoder circuit coupled to the MWD circuitry.

15. The semiconductor device of claim 12 wherein the peripheral circuitry further comprises an address decoder circuit.

16. The semiconductor device of claim 12 wherein each base semiconductor portion comprises silicon, and wherein the at least one non-semiconductor monolayer comprises oxygen.

17. A method for making a semiconductor device comprising:
forming a plurality of volatile memory cells;
forming peripheral circuitry coupled to the plurality of volatile memory cells and comprising a plurality of low threshold voltage (Vt) transistors configured to provide high speed operation during a first operating mode and a plurality of high Vt transistors configured as headers to reduce leakage in the low Vt transistors during a second operating mode, the high Vt and low Vt transistors each comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
forming a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during the first operating mode; and
forming a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a the second operating mode;
wherein the peripheral circuitry is operable at a first clock rate during the first operating mode and a second clock rate lower than the first clock rate during the second operating mode, and wherein data stored in the plurality of volatile memory cells is fully refreshed during the second operating mode.

18. The method of claim 17 wherein the first operating mode comprises an active mode, and wherein the second operating mode comprises a standby mode.

19. The method of claim 17 wherein the peripheral circuitry comprises a sense amplifier.

20. The method of claim 17 wherein the peripheral circuitry comprises a main wordline decoder (MWD) circuit.

21. The method of claim 20 wherein the peripheral circuitry further comprises a wordline pre-decoder circuit coupled to the MWD circuitry.

22. The method of claim 17 wherein the peripheral circuitry comprises an address decoder circuit.

23. The method of claim 17 wherein each base semiconductor portion comprises silicon, and wherein the at least one non-semiconductor monolayer comprises oxygen.

Assignees

• Atomera Inc

Inventors

• Roy Richard Stephen

Classifications

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C2207/2227

  Standby or low power modes · CPC title