Semiconductor device including a superlattice providing metal work function tuning
US-2026068244-A1 · Mar 5, 2026 · US
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Mears Robert J patents
Mears Robert J is listed as an inventor on 119 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Mears Robert J |
| Total patents | 119 |
| First publication | Nov 17, 2016 |
| Latest publication | Mar 5, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Methods for making surface acoustic wave (saw) devices including a superlattice
US-2025373219-A1 · Dec 4, 2025 · US
Surface acoustic wave (saw) devices including a superlattice and related methods
US-2025373225-A1 · Dec 4, 2025 · US
Radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice
US-2025372372-A1 · Dec 4, 2025 · US
Semiconductor device including a superlattice providing metal work function tuning
US-12439658-B2 · Oct 7, 2025 · US
Radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
US-12417912-B2 · Sep 16, 2025 · US
Method for making semiconductor device including superlattice source/drain
US-2025248090-A1 · Jul 31, 2025 · US
Semiconductor device including superlattice source/drain
US-2025248091-A1 · Jul 31, 2025 · US
Method for making semiconductor devices with group iii-n and silicon device regions above a superlattice layer
US-2025239448-A1 · Jul 24, 2025 · US
Semiconductor devices with group iii-n and silicon device regions above a superlattice layer and related methods
US-2025241034-A1 · Jul 24, 2025 · US
Recent patents
Latest publications not already listed above.
Method for making semiconductor devices including compound semiconductor materials with a superlattice layer
US-2025241018-A1 · Jul 24, 2025 · US
Semiconductor devices including compound semiconductor materials with a superlattice layer
US-2025241035-A1 · Jul 24, 2025 · US
Method for making semiconductor devices including compound semiconductor materials using a superlattice separation layer
US-2025239447-A1 · Jul 24, 2025 · US
Piezoelectric devices including compound semiconductor materials and a superlattice layer
US-2025241033-A1 · Jul 24, 2025 · US
Method of fabricating semiconductor devices with isolated superlattice structures
US-2025125149-A1 · Apr 17, 2025 · US
Methods for making semiconductor transistor devices with recessed superlattice over well regions
US-2025125187-A1 · Apr 17, 2025 · US
DRAM sense amplifier architecture with reduced power consumption and related methods
US-12267996-B2 · Apr 1, 2025 · US
Method for making a semiconductor device using superlattices with different non-semiconductor thermal stabilities
US-2025105021-A1 · Mar 27, 2025 · US
Method for making gate-all-around (gaa) device including a superlattice
US-2025048701-A1 · Feb 6, 2025 · US
Method for making a semiconductor superlattices with different non-semiconductor thermal stabilities
US-12191160-B2 · Jan 7, 2025 · US
Method for making semiconductor device including superlattice with oxygen and carbon monolayers
US-2025006794-A1 · Jan 2, 2025 · US
Method for making gate-all-around (GAA) device including a superlattice
US-12142641-B2 · Nov 12, 2024 · US
Method for making semiconductor device including superlattice with oxygen and carbon monolayers
US-12119380-B2 · Oct 15, 2024 · US
Radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice
US-2024321575-A1 · Sep 26, 2024 · US
Methods for making radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice
US-2024304443-A1 · Sep 12, 2024 · US
Radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
US-12020926-B2 · Jun 25, 2024 · US
Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
US-12014923-B2 · Jun 18, 2024 · US
Gate-all-around (gaa) device including a superlattice
US-2024194740-A1 · Jun 13, 2024 · US
Gate-all-around (GAA) device including a superlattice
US-11978771-B2 · May 7, 2024 · US
Method for making semiconductor device including superlattice with oxygen and carbon monolayers
US-2024063268-A1 · Feb 22, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Atomera Inc | 121 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D62/8162 | 113 |
| H10P14/3252 | 66 |
| H10D30/751 | 66 |
| H10P14/3211 | 54 |
| H01L29/152 | 53 |