Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control

Patent metadata

Field	Value
Publication number	US-2016358773-A1
Application number	US-201615169983-A
Country	US
Kind code	A1
Filing date	Jun 1, 2016
Priority date	Jun 2, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A method for processing a semiconductor wafer in a single wafer processing chamber may include heating the single wafer processing chamber to a temperature in a range of 650-700° C., and forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Depositing the oxygen may include depositing the oxygen using an N 2 O gas flow.

First claim

That which is claimed is:

1 . A method for processing a semiconductor wafer in a single wafer processing chamber, the method comprising:
heating the single wafer processing chamber to a temperature in a range of 650-700° C.; and forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; wherein depositing the oxygen comprises depositing the oxygen using an N 2 O gas flow.

2 . The method of claim 1 wherein the N 2 O gas flow comprises 0.1 to 10 N 2 O in a gas comprising at least one of He and Ar.

3 . The method of claim 1 wherein depositing the oxygen comprises depositing the oxygen with an exposure time in a range of 1 to 100 seconds.

4 . The method of claim 1 wherein the N 2 O gas flow is in a range of 10 to 5000 standard cubic centimeters per minute (SCCM).

5 . The method of claim 1 wherein depositing the oxygen comprises depositing the oxygen at a pressure in a range of 10 to 100 Torr.

6 . The method of claim 1 wherein a total dose of N 2 O is in a range of 1×10 14 to 7×10 14 atoms/cm 2 during the oxygen monolayer formation.

7 . The method of claim 1 wherein the semiconductor wafer comprises a plurality of spaced apart shallow trench isolation (STI) regions, and wherein forming the at least one superlattice comprises selectively forming a respective superlattice between adjacent pairs of STI regions.

8 . The method of claim 1 wherein forming the at least one superlattice comprises a blanket superlattice formation on the semiconductor wafer.

9 . The method of claim 1 wherein at least some silicon atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

10 . A method for processing a semiconductor wafer in a single wafer processing chamber, the semiconductor wafer comprising a plurality of spaced apart shallow trench isolation (STI) regions, the method comprising:
heating the single wafer processing chamber to a temperature in a range of 650-700° C.; and selectively forming a respective superlattice between adjacent pairs of STI regions on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; wherein depositing the oxygen comprises depositing the oxygen using an N 2 O gas flow and at a pressure in a range of 10 to 100 Torr.

11 . The method of claim 10 wherein the N 2 O gas flow comprises 0.1% to 10% N 2 O in a gas comprising at least one of He and Ar.

12 . The method of claim 10 wherein depositing the oxygen comprises depositing the oxygen with an exposure time in a range of 1 to 100 seconds.

13 . The method of claim 10 wherein the N 2 O gas flow is in a range of 10 to 5000 standard cubic centimeters per minute (SCCM).

14 . The method of claim 10 wherein a total dose of N 2 O is in a range of 1×10 14 to 7×10 14 atoms/cm 2 during the oxygen monolayer formation.

15 . The method of claim 10 wherein at least some silicon atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

16 . A method for processing a semiconductor wafer in a single wafer processing chamber, the method comprising:
heating the single wafer processing chamber to a temperature in a range of 650-700° C.; and forming a blanket superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; wherein depositing the oxygen comprises depositing the oxygen using an N 2 O gas flow and at a pressure in a range of 10 to 100 Torr.

17 . The method of claim 16 wherein the N 2 O gas flow comprises 0.1% to 10% N 2 O in a gas comprising at least one of He and Ar.

18 . The method of claim 16 wherein depositing the oxygen comprises depositing the oxygen with an exposure time in a range of 1 to 100 seconds.

19 . The method of claim 16 wherein the N 2 O gas flow is in a range of 10 to 5000 standard cubic centimeters per minute (SCCM).

20 . The method of claim 16 wherein a total dose of N 2 O is in a range of 1×10 14 to 7×10 14 atoms/cm 2 during the oxygen monolayer formation.

21 . The method of claim 16 wherein at least some silicon atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.

Assignees

• Atomera Inc

Inventors

• Mears Robert J
• Cody Nyles
• Stephenson Robert John

Classifications

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3252 Primary

  Alternating layers, e.g. superlattice · CPC title

• H10D62/8162

  having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation · CPC title

• H10D62/8161 Primary

  potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices (lateral superlattices, lateral surface superlattices H10D62/8181) · CPC title