Vertical semiconductor device with enhanced contact structure and associated methods

Patent metadata

Field	Value
Publication number	US-11664427-B2
Application number	US-202217750683-A
Country	US
Kind code	B2
Filing date	May 23, 2022
Priority date	Mar 8, 2018
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.

First claim

That which is claimed is:

1. A vertical semiconductor device comprising:
a semiconductor substrate having at least one trench therein;
a superlattice layer extending vertically adjacent the at least one trench, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a doped semiconductor layer adjacent the superlattice layer; and
a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.

2. The vertical semiconductor device of claim 1 wherein the conductive body comprises silicide.

3. The vertical semiconductor device of claim 1 wherein the conductive body comprises a metal liner adjacent the doped semiconductor layer and comprising a first metal, and a metal body adjacent the metal liner comprising a second metal.

4. The vertical semiconductor device of claim 3 wherein the doped semiconductor layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.

5. The vertical semiconductor device of claim 3 wherein the second metal comprises tungsten.

6. The vertical semiconductor device of claim 1 wherein the base semiconductor monolayers comprise silicon.

7. The vertical semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

8. The vertical semiconductor device of claim 1 wherein the superlattice layer also extends laterally adjacent a bottom of the at least one trench.

9. The vertical semiconductor device of claim 1 wherein the at least one trench comprises a plurality of trenches.

10. A vertical semiconductor device comprising:
a semiconductor substrate having at least one trench therein;
a superlattice layer extending vertically adjacent the at least one trench, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a doped semiconductor layer adjacent the superlattice layer; and
a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact, the conductive body comprising
a titanium liner adjacent the doped semiconductor layer, and
a tungsten body adjacent the titanium liner.

11. The vertical semiconductor device of claim 10 wherein the conductive body comprises silicide.

12. The vertical semiconductor device of claim 10 wherein the doped semiconductor layer comprises silicon.

13. The vertical semiconductor device of claim 10 wherein the base semiconductor monolayers comprise silicon.

14. The vertical semiconductor device of claim 10 wherein the at least one non-semiconductor monolayer comprises oxygen.

15. The vertical semiconductor device of claim 10 wherein the superlattice layer also extends laterally adjacent a bottom of the at least one trench.

16. The vertical semiconductor device of claim 10 wherein the at least one trench comprises a plurality of trenches.

17. A vertical semiconductor device comprising:
a semiconductor substrate having at least one trench therein;
a superlattice layer extending vertically adjacent the at least one trench, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer, with each at least one oxygen monolayer of each group of layers being constrained within a crystal lattice of adjacent base silicon portions;
a doped semiconductor layer on the superlattice layer; and
a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.

18. The vertical semiconductor device of claim 17 wherein the conductive body comprises silicide.

19. The vertical semiconductor device of claim 17 wherein the conductive body comprises a metal liner adjacent the doped semiconductor layer and comprising a first metal, and a metal body adjacent the metal liner comprising a second metal.

20. The vertical semiconductor device of claim 19 wherein the doped semiconductor layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.

21. The vertical semiconductor device of claim 19 wherein the second metal comprises tungsten.

22. The vertical semiconductor device of claim 17 wherein the superlattice layer also extends laterally adjacent a bottom of the at least one trench.

23. The vertical semiconductor device of claim 17 wherein the at least one trench comprises a plurality of trenches.

24. A method for making a vertical semiconductor device comprising:
forming at least one trench in a semiconductor substrate;
forming a superlattice layer extending vertically adjacent the at least one trench, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
forming a doped semiconductor layer adjacent the superlattice layer; and
forming a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.

25. The method of claim 24 wherein the conductive body comprises silicide.

26. The method of claim 24 wherein the conductive body comprises a metal liner adjacent the doped semiconductor layer and comprising a first metal, and a metal body adjacent the metal liner comprising a second metal.

27. The method of claim 26 wherein the doped semiconductor layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.

28. The method of claim 26 wherein the second metal comprises tungsten.

29. The method of claim 24 wherein the base semiconductor monolayers comprise silicon.

30. The method of claim 24 wherein the at least one non-semiconductor monolayer comprises oxygen.

31. The method of claim 24 wherein the superlattice layer also extends laterally adjacent a bottom of the at least one trench.

32. The method of claim 24 wherein the at least one trench comprises a plurality of trenches.

Assignees

• Atomera Inc

Inventors

• Stephenson Robert John
• Burton Richard
• Choutov Dmitri
• Cody Nyles Wynn
• Connelly Daniel
• Mears Robert J
• Trautmann Erwin

Classifications

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title