Semiconductor devices including superlattice depletion layer stack and related methods

Patent metadata

Field	Value
Publication number	US-9406753-B2
Application number	US-201414550272-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Nov 22, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.

First claim

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming an alternating stack of a plurality of superlattices and a plurality of bulk semiconductor layers on a substrate, each superlattice including a plurality of stacked group of layers, each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
doping bulk semiconductor layers between respective superlattices with alternating dopant conductivity types defining a p-n junction;
forming spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattices and bulk semiconductor layers; and
forming a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions and defining a depleted channel between the source and drain regions and above the p-n junction;
wherein the semiconductor device is substantially devoid of an oxide layer between the channel and the substrate.

2. The method of claim 1 further comprising forming at least one shallow trench isolation (STI) region extending through the alternating stack of superlattice and bulk semiconductor layers and into the substrate.

3. The method of claim 1 wherein each base semiconductor portion comprises silicon.

4. The method of claim 1 wherein each base semiconductor portion comprises germanium.

5. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

6. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

7. The method of claim 1 wherein forming the gate comprises forming an oxide layer on the upper bulk semiconductor layer between the spaced apart source and drain regions, and forming a gate electrode overlying the oxide layer.

8. The method of claim 1 wherein less than half of the possible sites available for non-semiconductor atoms in each non-semiconductor monolayer to bond with semiconductor atoms from adjacent base semiconductor monolayers are occupied by non-semiconductor atoms.

9. A semiconductor device comprising:
an alternating stack of a plurality of superlattices and a plurality of bulk semiconductor layers on a substrate, each superlattice including a plurality of stacked group of layers, each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, the bulk semiconductor layers between respective superlattices being doped with alternating dopant conductivity types defining a p-n junction;
spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattices and bulk semiconductor layers; and
a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions and defining a depleted channel between the source and drain regions and above the p-n junction;
wherein the semiconductor device is substantially devoid of an oxide layer between the channel and the substrate.

10. The semiconductor device of claim 9 further comprising at least one shallow trench isolation (STI) region extending through the alternating stack of superlattice and bulk semiconductor layers and into the substrate.

11. The semiconductor device of claim 9 wherein each base semiconductor portion comprises silicon.

12. The semiconductor device of claim 9 wherein each base semiconductor portion comprises germanium.

13. The semiconductor device of claim 9 wherein the at least one non-semiconductor monolayer comprises oxygen.

14. The semiconductor device of claim 9 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

15. The semiconductor device of claim 9 wherein the gate comprises an oxide layer on the upper bulk semiconductor layer between the spaced apart source and drain regions, and a gate electrode overlying the oxide layer.

16. The semiconductor device of claim 9 wherein less than half of the possible sites available for non-semiconductor atoms in each non-semiconductor monolayer to bond with semiconductor atoms from adjacent base semiconductor monolayers are occupied by non-semiconductor atoms.

17. A semiconductor device comprising:
an alternating stack of a plurality of superlattices and a plurality of bulk silicon layers on a substrate, each superlattice including a plurality of stacked group of layers, each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, the bulk semiconductor layers between respective superlattices being doped with alternating dopant conductivity types defining a p-n junction;
spaced apart source and drain regions in an upper bulk silicon layer of the alternating stack of superlattices and bulk silicon layers; and
a gate on the upper bulk silicon layer between the spaced apart source and drain regions and defining a depleted channel between the source and drain regions and above the p-n junction;
wherein the semiconductor device is substantially devoid of an oxide layer between the channel and the substrate.

18. The semiconductor device of claim 17 further comprising at least one shallow trench isolation (STI) region extending through the alternating stack of superlattices and bulk silicon layers and into the substrate.

19. The method of claim 1 wherein the channel is partially depleted.

20. The method of claim 1 wherein the channel is fully depleted.

21. The semiconductor device of claim 9 wherein the channel is partially depleted.

22. The semiconductor device of claim 9 wherein the channel is fully depleted.

Assignees

• Atomera Inc

Inventors

• Mears Robert
• Takeuchi Hideki
• Trautmann Erwin

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title