Method for making a semiconductor device including enhanced contact structures having a superlattice

Patent metadata

Field	Value
Publication number	US-10879356-B2
Application number	US-201916296400-A
Country	US
Kind code	B2
Filing date	Mar 8, 2019
Priority date	Mar 8, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.

First claim

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming a trench in a semiconductor substrate;
forming a superlattice liner at least partially covering bottom and sidewall portions of the trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
forming a semiconductor cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
forming a conductive body within the trench.

2. The method of claim 1 wherein forming the conductive body comprises forming a metal liner adjacent the semiconductor cap layer and comprising a first metal; and forming a metal body adjacent the metal liner, filling the trench and comprising a second metal.

3. The method of claim 2 wherein forming the conductive body further comprises annealing the metal liner.

4. The method of claim 3 wherein annealing the metal liner at least partially consumes the superlattice liner.

5. The method of claim 3 wherein the semiconductor cap layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.

6. The method of claim 5 wherein the second metal comprises tungsten.

7. The method of claim 1 further comprising cleaning the semiconductor cap layer prior to forming the conductive body within the recess.

8. The method of claim 1 wherein the conductive body defines a source/drain contact.

9. The method of claim 1 wherein the base semiconductor monolayers comprise silicon.

10. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

11. The method of claim 1 further comprising implanting the dopant in the semiconductor cap layer using an implant energy in a range of 2-20 keV.

12. The method of claim 1 wherein the dopant comprises at least one of boron, arsenic, and phosphorus.

13. A method for making a semiconductor device comprising:
forming a trench in a semiconductor substrate;
forming a superlattice liner at least partially covering bottom and sidewall portions of the trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
forming a semiconductor cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
forming a conductive body within the trench by
forming a metal liner adjacent the semiconductor cap layer and comprising titanium, and
forming a tungsten body adjacent the metal liner and filling the trench.

14. The method of claim 13 wherein forming the conductive body further comprises annealing the metal liner.

15. The method of claim 14 wherein annealing the metal liner at least partially consumes the superlattice liner.

16. The method of claim 13 further comprising cleaning the semiconductor cap layer prior to forming the conductive body within the recess.

17. The method of claim 13 wherein the conductive body defines a source/drain contact.

18. A method for making a semiconductor device comprising:
forming a trench in a semiconductor substrate;
forming a superlattice liner at least partially covering bottom and sidewall portions of the trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
forming a silicon cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
forming a conductive body within the trench.

19. The method of claim 18 wherein forming the conductive body comprises forming a metal liner adjacent the silicon cap layer and comprising a first metal; and forming a metal body adjacent the metal liner, filling the trench and comprising a second metal.

20. The method of claim 19 wherein forming the conductive body further comprises annealing the metal liner.

21. The method of claim 20 wherein annealing the metal liner at least partially consumes the superlattice liner.

22. The method of claim 20 wherein the semiconductor cap layer comprises silicon, and the first metal comprises at least one of titanium, cobalt and nickel.

23. The method of claim 22 wherein the second metal comprises tungsten.

24. The method of claim 18 wherein the conductive body defines a source/drain contact.

25. A method for making a semiconductor device comprising:
forming a trench in a semiconductor substrate;
forming a superlattice liner at least partially covering bottom and sidewall portions of the trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
forming a semiconductor cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
forming a conductive body within the trench comprising forming a metal liner adjacent the semiconductor cap layer and comprising a first metal; and forming a metal body adjacent the metal liner, filling the trench and comprising a second metal.

26. The method of claim 25 wherein forming the conductive body further comprises annealing the metal liner.

Assignees

• Atomera Inc

Inventors

• Stephenson Robert John
• Burton Richard
• Choutov Dmitri
• Cody Nyles Wynn
• Connelly Daniel
• Mears Robert J
• Trautmann Erwin

Classifications

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title