Semiconductor device including enhanced contact structures having a superlattice

Patent metadata

Field	Value
Publication number	US-10777451-B2
Application number	US-201916296414-A
Country	US
Kind code	B2
Filing date	Mar 8, 2019
Priority date	Mar 8, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.

First claim

That which is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a trench therein;
a superlattice liner at least partially covering bottom and sidewall portions of the trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a semiconductor cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the trench.

2. The semiconductor device of claim 1 wherein the conductive body comprises a metal liner adjacent the semiconductor cap layer and comprising a first metal, and a metal body adjacent the metal liner, filling the trench and comprising a second metal.

3. The semiconductor device of claim 2 wherein the conductive body further comprises silicide.

4. The semiconductor device of claim 2 wherein the semiconductor cap layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.

5. The semiconductor device of claim 4 wherein the second metal comprises tungsten.

6. The semiconductor device of claim 1 wherein the conductive body defines a source/drain contact.

7. The semiconductor device of claim 1 wherein the base semiconductor monolayers comprise silicon.

8. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

9. The semiconductor device of claim 1 wherein the dopant comprises at least one of boron, arsenic, and phosphorus.

10. A semiconductor device comprising:
a semiconductor substrate having a trench therein;
a superlattice liner at least partially covering bottom and sidewall portions of the trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a semiconductor cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the trench and comprising
a metal liner adjacent the semiconductor cap layer and comprising titanium, and
a tungsten body adjacent the metal liner and filling the trench.

11. The semiconductor device of claim 10 wherein the conductive body further comprises silicide.

12. The semiconductor device of claim 11 wherein the semiconductor cap layer comprises silicon.

13. The semiconductor device of claim 10 wherein the conductive body defines a source/drain contact.

14. The semiconductor device of claim 10 wherein the base semiconductor monolayers comprise silicon.

15. The semiconductor device of claim 10 wherein the at least one non-semiconductor monolayer comprises oxygen.

16. The semiconductor device of claim 10 wherein the dopant comprises at least one of boron, arsenic, and phosphorus.

17. A semiconductor device comprising:
a semiconductor substrate having a trench therein;
a superlattice liner at least partially covering bottom and sidewall portions of the trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base silicon portions;
a semiconductor cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the trench.

18. The semiconductor device of claim 17 wherein the conductive body comprises a metal liner adjacent the semiconductor cap layer and comprising a first metal, and a metal body adjacent the metal liner, filling the trench and comprising a second metal.

19. The semiconductor device of claim 18 wherein the conductive body further comprises silicide.

20. The semiconductor device of claim 18 wherein the semiconductor cap layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.

21. The semiconductor device of claim 20 wherein the second metal comprises tungsten.

22. The semiconductor device of claim 17 wherein the conductive body defines a source/drain contact.

23. The semiconductor device of claim 17 wherein the dopant comprises at least one of boron, arsenic, and phosphorus.

24. A semiconductor device comprising:
a semiconductor substrate having a trench therein;
a superlattice liner at least partially covering bottom and sidewall portions of the trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a semiconductor cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the trench comprising a metal liner adjacent the semiconductor cap layer and comprising a first metal, and a metal body adjacent the metal liner, filling the trench and comprising a second metal.

25. The semiconductor device of claim 24 wherein the conductive body further comprises silicide.

26. A semiconductor device comprising:
a semiconductor substrate having a trench therein;
a superlattice liner at least partially covering bottom and sidewall portions of the trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a semiconductor cap layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the trench defining a source/drain contact.

27. The semiconductor device of claim 26 wherein the conductive body further comprises silicide.

Assignees

• Atomera Inc

Inventors

• Stephenson Robert John
• Burton Richard
• Choutov Dmitri
• Cody Nyles Wynn
• Connelly Daniel
• Mears Robert J
• Trautmann Erwin

Classifications

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title