Semiconductor package with plateable encapsulant and a method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10396007-B2
Application number	US-201715448018-A
Country	US
Kind code	B2
Filing date	Mar 2, 2017
Priority date	Mar 3, 2016
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.

First claim

What is claimed is:

1. A package, comprising:
a first encapsulant configured so that electrically conductive material is plateable thereon;
a second encapsulant configured so that electrically conductive material is not plateable thereon;
a redistribution layer at least partially encapsulated by one of the first encapsulant and the second encapsulant;

wherein at least part of an exposed outer lateral sidewall of the first encapsulant is plated with the electrically conductive material for providing an electrically conductive coupling to the redistribution layer,
wherein the first encapsulate comprise an active portion which is activated for enabling plating of the electrically conductive material and a non-active portion which is deactivated for disabling plating of the electrically conductive material.

2. The package according to claim 1 , comprising at least one semiconductor chip at least partially encapsulated in one of the first encapsulant and the second encapsulant.

3. The package according to claim 1 , comprising at least one antenna structure at least partially on and/or in at least one of the first encapsulant and the second encapsulant, in particular at least partially located at a surface of the package.

4. The package according to claim 1 , wherein at least one of the first encapsulant and the second encapsulant is a mold compound with activated or deactivated organometallic cluster component, more particularly organometallic polymer cluster component, in a mold matrix.

5. The package according to claim 1 , wherein at least part of a surface of the first encapsulant is plated with electrically conductive material.

6. The package according to claim 5 , comprising the following feature:
at least part of a planar wall of the first encapsulant is plated with a planar layer of electrically conductive material.

7. The package according to claim 5 , wherein the plated electrically conductive material is configured for at least one of the group consisting of:
for electrically connecting at least one semiconductor chip with at least one antenna structure;
for providing an electromagnetic interference shielding of the package;
for electrically connecting at least one semiconductor chip with at least one solder structure.

8. The package according to claim 1 , wherein at least part of the second encapsulant is configured as at least one vertically extending isolation bar vertically protruding into the first encapsulant, in particular at least one vertically extending isolation bar forming at least one corner section of the package.

9. A method of manufacturing a package, the method comprising:
configuring a first encapsulant so that electrically conductive material is plateable thereon;
configuring a second encapsulant so that electrically conductive material is not plateable thereon;
plating, in particular electroless plating, electrically conductive material selectively on a surface of the first encapsulant without plating electrically conductive material on a surface of the second encapsulant;
providing a redistribution layer at least partially encapsulated by any one of the first encapsulant and second encapsulant;
plating at least part of an exposed outer lateral sidewall of the first encapsulant with the electrically conductive material for providing an electrically conductive coupling to the redistribution layer,
wherein the first encapsulate comprise an active portion which is activated for enabling plating of the electrically conductive material and a non-active portion which is deactivated for disabling plating of the electrically conductive material.

10. The method according to claim 9 , wherein a surface, in particular the sidewall, of the first encapsulant is exposed before the plating, in particular is exposed by sawing while the first encapsulant and the second encapsulant of the package are arranged on a temporary carrier.

11. The package according to claim 2 , further comprising
an electronic periphery at least partially located at a surface of the package;

wherein the redistribution layer is electrically coupled to the semiconductor chip;
wherein the electronic periphery is configured electrically coupled to the semiconductor chip via the exposed outer side wall of the first encapsulant plated with the electrically conductive material.

12. The package according to claim 1 , wherein the active portion comprises transition metal particles being in an electrically conductive neutral charging state, in particular active palladium in a Pd0 charging state.

13. The package according to claim 1 , wherein the first encapsulant comprises an inactive material, in particular an electrically insulating inactive material, covering the plating catalyst in the non-active portion.

Assignees

• Infineon Technologies Ag

Inventors

• Chan Sook Woon
• Chiang Chau Fatt
• Chua Kok Yau
• Goh Soon Lock
• Lee Swee Kah
• Mahler Joachim
• Ng Mei Chin
• See Beng Keh
• Tee Guan Choon Matthew Nelson

Classifications

• H10W42/284

  shielding resins · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/07255

  changes in materials · CPC title