Semiconductor package structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2018114762-A1
Application number	US-201615299236-A
Country	US
Kind code	A1
Filing date	Oct 20, 2016
Priority date	Oct 20, 2016
Publication date	Apr 26, 2018
Grant date	—

Abstract

A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

First claim

What is claimed is:

1 . A semiconductor package structure, comprising:
a substrate; a semiconductor element disposed on the substrate; an encapsulant covering the semiconductor element; an adhesion layer disposed on the encapsulant; and a metal cap attached to the encapsulant by the adhesion layer, wherein the metal cap is conformal with the encapsulant.

2 . The semiconductor package structure according to claim 1 , wherein a material of the encapsulant is a molding compound.

3 . The semiconductor package structure according to claim 1 , wherein a material of the adhesion layer is a solder mask.

4 . The semiconductor package structure according to claim 1 , wherein the adhesion layer is formed from a thermosetting resin or a photosetting resin.

5 . The semiconductor package structure according to claim 1 , wherein a material of the adhesion layer includes an interpenetrating polymer network structure.

6 . The semiconductor package structure according to claim 1 , wherein the metal cap includes at least one metal layer.

7 . The semiconductor package structure according to claim 6 , wherein a material of the metal layer is selected from a group consisting of silver, copper, gold, aluminum, zinc, brass, cadmium, nickel, phosphor bronze, iron, steel, stainless steel, and combinations thereof.

8 . The semiconductor package structure according to claim 1 , wherein the metal cap includes an extending portion attached to a side surface of the substrate.

9 . The semiconductor package structure according to claim 8 , wherein the metal cap includes a grounding pin, and the grounding pin connects to the extending portion.

10 . The semiconductor package structure according to claim 1 , wherein the metal cap includes at least two metal layers, and materials of the metal layers are different.

11 . The semiconductor package structure according to claim 1 , wherein the encapsulant includes a first surface and a side surface, the adhesion layer includes a first portion and a side portion, the metal cap includes a first portion and a side portion, the first portion of the metal cap is attached to the first surface of the encapsulant by the first portion of the adhesion layer, and the side portion of the metal cap is attached to the side surface of the encapsulant by the side portion of the adhesion layer.

12 . The semiconductor package structure according to claim 1 , wherein the metal cap includes a first portion and a side portion, and the first portion defines an opening to expose a portion of the adhesion layer.

13 . A method for manufacturing a semiconductor package structure, comprising:
(a) providing a substrate with a semiconductor element disposed thereon; and (b) providing an encapsulant, an adhesion layer and a metal cap to form the semiconductor package structure, wherein the encapsulant covers the semiconductor element, the adhesion layer is disposed on the encapsulant, the metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

14 . The method according to claim 13 , further comprising:
(c) baking the semiconductor package structure.

15 . The method according to claim 13 , wherein (b) includes:
(b1) forming the encapsulant on the substrate to cover the semiconductor element; (b2) providing a metal foil; (b3) forming the adhesion layer on a surface of the metal foil; (b4) disposing the metal foil above the encapsulant, wherein the adhesion layer faces the encapsulant; and (b5) punching the metal foil to the encapsulant, so as to form the metal cap attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

16 . The method according to claim 15 , wherein, after (b1), the method further includes:
(b11) curing the encapsulant.

17 . The method according to claim 13 , wherein (b) includes:
(b1) providing the metal cap, wherein the metal cap defines a cavity, and the adhesion layer is disposed on the metal cap in the cavity; (b2) dispensing an encapsulant material in the cavity; (b3) disposing the substrate adjacent to the metal cap, wherein the semiconductor element faces the encapsulant material; and (b4) pressing the substrate to the metal cap, so that the encapsulant material covers the semiconductor element to form the encapsulant, the metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

18 . The method according to claim 13 , wherein (b) includes:
(b1) forming the encapsulant on the substrate to cover the semiconductor element; (b2) curing the encapsulant; (b3) forming the adhesion layer on a surface of the encapsulant; (b4) providing a metal foil; (b5) disposing the metal foil above the encapsulant and the adhesion layer; and (b6) punching the metal foil to the encapsulant, so as to form the metal cap attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

19 . The method according to claim 18 , wherein, after (b2), the method further includes:
(b21) providing a mask defining an opening; and (b22) disposing the substrate in the opening of the mask; wherein, after (b3), the method further includes: (b31) removing the mask.

20 . The method according to claim 13 , wherein a material of the adhesion layer is a solder mask, the metal cap includes at least one metal layer, a material of the metal layer is selected from a group consisting of silver, copper, gold, aluminum, zinc, brass, cadmium, nickel, phosphor bronze, iron, steel, stainless steel, and combinations thereof.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chiu Ying-Ta
• Lee Chiu-Wen
• Chen Dao-Long
• Sung Po-Hsien
• Yang Ping-Feng
• Lin Kwang-Lung

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W76/10

  Containers or parts thereof · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title