Selective planishing method for making a semiconductor device

Patent metadata

Field	Value
Publication number	US-2015221526-A1
Application number	US-201514684848-A
Country	US
Kind code	A1
Filing date	Apr 13, 2015
Priority date	May 2, 2012
Publication date	Aug 6, 2015
Grant date	—

Abstract

In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

First claim

I claim:

1 - 18 . (canceled)

19 . A method for fabricating a plurality of semiconductor devices, said method comprising:
forming a leadframe pattern from a flat tape of base metal; plating a plurality of additional metal layers on the patterned tape of base metal; roughening the surface of the metal layers; creating a plurality of sites for assembling semiconductor chips, the sites alternating with zones for connecting the leadframe pattern to molding compound runners; selectively planishing a selected first set of leadframe areas creating flattened areas offsetting a second set of leadframe areas; and attaching a semiconductor chip to each site.

20 . The method of claim 19 further including roughing the surfaces of the sites on both sides of the leadframe.

21 . The method of claim 20 further including selectively planishing the surfaces of the zones on both sides of the leadframe.

22 . The method of claim 20 wherein the rough metal surfaces have an average roughness of 90±20 nm, enhancing the adhesion of the leadframe metal to a molding compound.

23 . The method of claim 21 wherein the flattened areas created by the have an average roughness of 35±20 nm, reducing the adhesion of the leadframe metal to a molding compound.

24 . The method of claim 23 wherein the planishing process creating the flattened areas causes a thickness reduction of the rough surface leadframe metal by 10±5%.

25 . The method of claim 19 wherein the flattened areas transitioning into the rough surface portions by a step.

26 . The method of claim 25 wherein the step spacing the flattened surface portions from the rough surface portions equals the thickness reduction of the rough surface leadframe metal.

27 . The method of claim 26 , further comprising cutting tape into strips

28 . The method of claim 19 wherein the rough metal surfaces have been created by a flood roughening method.

29 . The method of claim 19 wherein the rough metal surfaces have been created by a mechanical roughening method.

30 . A method of fabricating semiconductor device comprising:
forming a leadframe having a pad with a plurality of straps, and a plurality of leads including first and second portions, each one of the plurality of straps has an end; roughing the pad, the plurality of straps, and the plurality of the leads; attaching a semiconductor chip to the pad; wire bonding the semiconductor chip to the first lead portions; encapsulating with a compound the semiconductor chip, the pad, the plurality of straps, the bonding wires and the first lead portions, leaving the second lead portions un-encapsulated; exposing at least one of the plurality of strap ends; and selectively planishing a portion adjacent to the at least of the exposed ends.

31 . The method of claim 30 further including transitioning by a step into the rough surface of the remainder of the strap.

32 . The method of claim 30 , wherein roughing includes roughing both sides of the leadframe.

33 . The method of claim 30 , wherein planishing includes planishing both sides of the leadframe.

34 . The method of claim 30 wherein the rough metal surfaces have been created by a flood roughening method.

35 . The method of claim 30 wherein the rough metal surfaces have been created by a mechanical roughening method.

36 . The method of claim 30 wherein roughing is done to an average roughness of 90±20 nm, enhancing the adhesion of the leadframe metal to the encapsulating compound.

37 . The method of claim 36 , wherein the planishing process causes a thickness reduction of the rough-surface leadframe metal by 10±5%.

38 . The method of claim 37 wherein a step spacing the planished surface portions from the rough surface portions equals the thickness reduction of the rough-surface leadframe metal.

39 . The method of claim 30 wherein the strap portion at the strap end having a smooth surface extends about 15±5 μm inside from the strap end.

Assignees

• Texas Instruments Inc

Inventors

• Abbott Donald C

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10W72/951

  Materials of bond pads · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W70/438

  of side rails, e.g. having holes · CPC title