Thermal Management of Molded Packages

Patent metadata

Field	Value
Publication number	US-2018182736-A1
Application number	US-201615388906-A
Country	US
Kind code	A1
Filing date	Dec 22, 2016
Priority date	Dec 22, 2016
Publication date	Jun 28, 2018
Grant date	—

Abstract

An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.

First claim

What is claimed is:

1 . An apparatus comprising:
a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity.

2 . The apparatus of claim 1 , wherein:
the semiconductor die includes a major first axis; a second axis, parallel to the first axis, intersects the polymer; and the second axis intersects the package molding on opposing sides of the polymer.

3 . The apparatus of claim 2 , wherein the aperture includes sidewalls that are smooth.

4 . The apparatus of claim 3 , wherein the sidewalls are non-circular in a cross-section taken in a plane parallel to the first and second axes.

5 . The apparatus of claim 2 comprising a substrate wherein:
the semiconductor die is on the substrate;
the semiconductor die is configured to be electrically coupled to the substrate with a member selected from the group consisting of a bump interconnect and a wirebond;
the semiconductor die comprises a member selected from the group consisting of a transistor, a capacitor, and an inductor;
the semiconductor die is included in a die stack that includes additional semiconductor dies; and
the additional semiconductor dies are located between the semiconductor die and the substrate.

6 . The apparatus of claim 2 comprising a substrate, wherein:
the semiconductor die includes a second die surface, opposite the first die surface, which is between the semiconductor die and the substrate;
the semiconductor die is between the substrate and the package molding;
a third axis, orthogonal to the first and second axes, intersects the package molding and the semiconductor die but not the polymer; and
a fourth axis, parallel to the third axis, intersects the polymer and the semiconductor die but not the package molding.

7 . The apparatus of claim 2 wherein the first thermal conductivity is less than 1 W/(m·K) and the second thermal conductivity is greater than 3 W/(m·K).

8 . The apparatus of claim 2 , wherein:
the package molding comprises a polymer selected from the group consisting of a thermoset epoxy, a silicone, a thermoplastic polymer, a liquid crystal polymer, and mixtures thereof; and the polymer includes particles selected from the group consisting of metal particles and thermally conductive particles.

9 . The apparatus of claim 8 , wherein the particles form at least one of a percolated network and a sintered network.

10 . The apparatus of claim 2 wherein in a plane parallel to the first axis the polymer is completely surrounded by the package molding.

11 . The apparatus of claim 2 comprising:
an additional semiconductor die; and
additional package molding that is molded onto an additional first die surface of the additional semiconductor die and at least two additional sidewalls of the additional semiconductor die;
wherein: (b)(i) the semiconductor die includes a height measured orthogonal to the first axis and the additional semiconductor die includes an additional height that is unequal to the height of the semiconductor die, and (b)(ii) the package molding and the additional package molding are monolithic with each other.

12 . The apparatus of claim 11 , wherein
the additional package molding includes: (c)(i) an additional first surface contacting the additional semiconductor die, (c)(ii) an additional second surface opposite the additional first surface, and (c)(iii) an additional aperture that extends from the additional first surface to the additional second surface; and an additional polymer, substantially filling the additional aperture, that includes particles selected from the group consisting of metal particles and thermally conductive particles.

13 . The apparatus of claim 1 wherein the polymer directly contacts the semiconductor die.

14 . The apparatus of claim 1 comprising:
an additional semiconductor die;
additional package molding that is molded onto and conformal with an additional first die surface of the additional semiconductor die and at least two additional sidewalls of the additional semiconductor die, the additional package molding including: (b)(i) an additional first surface contacting the additional semiconductor die, (b)(ii) an additional second surface opposite the additional first surface, and (b)(iii) an additional aperture that extends from the additional first surface to the additional second surface; and
an additional polymer, substantially filling the additional aperture, that includes particles selected from the group consisting of metal particles and thermally conductive particles;
wherein: (c)(i) the semiconductor die includes a second die surface opposite the first die surface, (c)(ii) the additional semiconductor die includes an additional second die surface opposite the additional first die surface, (c)(iii) the second die surface and the additional second die surface are substantially coplanar with each other, and (c)(iv) the first die surface and the additional first die surface are not substantially coplanar with each other.

15 . The apparatus of claim 14 wherein the package molding includes a material having a material composition and the additional package molding includes an additional material having an additional material composition that is substantially equivalent to the material composition.

16 . The apparatus of claim 1 wherein:
the package molding includes at least one additional aperture that extends from the first surface to the second surface;
at least one additional polymer, substantially filling the at least one additional aperture, that includes additional particles selected from the group consisting of metal particles and thermally conductive particles; and
the additional particles form at least one of a percolated network and a sintered network.

17 . The apparatus of claim 1 comprising:
a substrate;
a first via included in the package molding; and
a second via included in the substrate;
wherein: (b)(i) the package molding includes a third surface between the semiconductor die and the substrate, (b)(ii) the first via couples the polymer to the second via through the third surface.

18 . The apparatus of claim 17 , wherein:
the semiconductor die includes a major first axis; and a second axis, orthogonal to the first axis, intersects the first via but not the semiconductor die.

19 . The apparatus of claim 1 comprising:
a substrate;
a first via included in the package molding;
wherein: (b)(i) the package molding includes a third surface between the semiconductor die and the substrate, (b)(ii) the first via couples the polymer to the third surface.

20 . The apparatus of claim 19 comprising:
an additional semiconductor die included within an additional package;
wherein: (c)(i) the semiconductor die includes a major first axis; (c)(ii) a second axis, orthogonal to the first axis, intersects the additional package and the first via but not the semiconductor die.

21 . The

Assignees

• Intel Corp

Inventors

• Eid Feras
• Abazarnia Nader N
• Swan Johanna M
• Beasley Taesha D
• Oster Sasha N
• Harirchian Tannaz
• Liff Shawna M

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/721

  of bump connectors · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title